http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47008
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |jakub at gcc dot gnu.org
--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> 2010-12-20
10:30:43 UTC ---
It doesn't, it looks like a RA/reload bug.
In *.sched1 we have:
17 NOTE_INSN_BASIC_BLOCK
31 [pre sp:DI+=0xfffffffffffffff8]=0
20 {r64:DI=frame:DI-0x30;clobber flags:CC;}
REG_UNUSED: flags:CC
23 r67:SI=0x20202020
24 r68:DI=0x6
18 [frame:DI-0x8]=r63:DI
19 [frame:DI-0x30]=0x1e23f
32 [pre sp:DI+=0xfffffffffffffff8]=0
21 {r65:DI=r64:DI+0x4;clobber flags:CC;}
REG_UNUSED: flags:CC
34 {r72:DI=frame:DI-0x8;clobber flags:CC;}
REG_UNUSED: flags:CC
29 r71:DI=0xa
36 r9:DI=`*.LC1'
37 r8:DI=`*.LC2'
25 {r68:DI=0;r66:DI=r68:DI<<0x2+r65:DI;[r65:DI]=0;use r67:SI;use r68:DI;}
REG_DEAD: r67:SI
REG_DEAD: r65:DI
REG_UNUSED: r68:DI
REG_UNUSED: r66:DI
so, the 0x1e23f store in insn 19 is to frame-48 and then there is memset
(frame-48+4, ' ', 24)
In *.ira this is:
17 NOTE_INSN_BASIC_BLOCK
31 [pre sp:DI+=0xfffffffffffffff8]=0
20 {si:DI=sp:DI+0x8;clobber flags:CC;}
REG_EQUIV: sp:DI+0x8
24 cx:DI=0x6
REG_EQUAL: 0x6
18 [sp:DI+0x30]=r10:DI
19 [sp:DI+0x8]=0x1e23f
32 [pre sp:DI+=0xfffffffffffffff8]=0
21 {dx:DI=si:DI+0x4;clobber flags:CC;}
34 {bx:DI=sp:DI+0x38;clobber flags:CC;}
REG_EQUIV: sp:DI+0x38
29 r11:DI=0xa
REG_EQUAL: 0xa
36 r9:DI=`*.LC1'
37 r8:DI=`*.LC2'
57 ax:SI=0x20202020
REG_EQUIV: 0x20202020
59 di:DI=dx:DI
25 {cx:DI=0;di:DI=cx:DI<<0x2+di:DI;[di:DI]=0;use ax:SI;use cx:DI;}
i.e. frame-48 is rsp+0 at the beginning of the bb, and the 0x1e234 store is to
that location and memset 4 bytes above it (as there are intervening push insns,
the store is to %rsp+8 at that point and memset is to %rsp+16+4). The
REG_EQUIV on insn 20 is wrong though, %rsi is equal to %rsp+8 only until %rsp
is changed, not always.
And in *.postreload it uses REG_EQUIV to optimize rdx = rsi + 4 into rdx = rsp
+ 12, which is wrong in that spot, it should have been rsp + 20:
31 [pre sp:DI+=0xfffffffffffffff8]=0
20 {si:DI=sp:DI+0x8;clobber flags:CC;}
REG_EQUIV: sp:DI+0x8
24 cx:DI=0x6
REG_EQUAL: 0x6
18 [sp:DI+0x30]=r10:DI
19 [sp:DI+0x8]=0x1e23f
32 [pre sp:DI+=0xfffffffffffffff8]=0
21 {dx:DI=sp:DI+0xc;clobber flags:CC;}
34 {bx:DI=sp:DI+0x38;clobber flags:CC;}
REG_EQUIV: sp:DI+0x38
29 r11:DI=0xa
REG_EQUAL: 0xa
36 r9:DI=`*.LC1'
37 r8:DI=`*.LC2'
57 ax:SI=0x20202020
REG_EQUIV: 0x20202020
59 di:DI=dx:DI
25 {cx:DI=0;di:DI=cx:DI<<0x2+di:DI;[di:DI]=0;use ax:SI;use cx:DI;}
