[Bug middle-end/45214] Poor initial RTL for bitfield operations

[pinskia at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45214

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|tree-optimization           |middle-end
               Host|i686-pc-linux-gnu           |
              Build|i686-pc-linux-gnu           |

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> 2010-10-28 
19:20:39 UTC ---
  D.2047_5 = t_1->gsbase.plf;
  D.2048_6 = (unsigned char) D.2047_5;
  D.2049_7 = D.2048_6 | 1;
  D.2050_8 = (<unnamed-unsigned:2>) D.2049_7;
  t_1->gsbase.plf = D.2050_8;


It could be optimized to just:
  D.2047_5 = t_1->gsbase.plf;
  D.2047_6 = D.2047_5 | 1
  t_1->gsbase.plf = D.2050_6;

But I will note that on MIPS64-Linux-gnu we get pretty good RTL at the
beginning due to zero_extract:

(insn 9 8 10 t.c:48 (set (reg:SI 201)
        (mem/s:SI (reg/v/f:SI 193 [ t ]) [0+0 S4 A32])) -1 (nil))

(insn 10 9 11 t.c:48 (set (reg:DI 203)
        (zero_extract:DI (subreg:DI (reg:SI 201) 0)
            (const_int 2 [0x2])
            (const_int 19 [0x13]))) -1 (nil))

(insn 11 10 12 t.c:48 (set (reg:QI 204)
        (truncate:QI (reg:DI 203))) -1 (nil))

(insn 12 11 13 t.c:48 (set (reg:SI 205)
        (ior:SI (subreg:SI (reg:QI 204) 0)
            (const_int 1 [0x1]))) -1 (nil))

(insn 13 12 14 t.c:48 (set (reg:SI 206)
        (mem/s/j:SI (reg/v/f:SI 193 [ t ]) [0+0 S4 A32])) -1 (nil))

(insn 14 13 15 t.c:48 (set (reg:DI 207)
        (subreg:DI (reg:SI 206) 0)) -1 (nil))

(insn 15 14 16 t.c:48 (set (zero_extract:DI (reg:DI 207)
            (const_int 2 [0x2])
            (const_int 19 [0x13]))
        (subreg:DI (reg:SI 205) 0)) -1 (nil))

(insn 16 15 17 t.c:48 (set (reg:SI 206)
        (truncate:SI (reg:DI 207))) -1 (nil))

(insn 17 16 0 t.c:48 (set (mem/s/j:SI (reg/v/f:SI 193 [ t ]) [0+0 S4 A32])
        (reg:SI 206)) -1 (nil))