[Bug rtl-optimization/45472] [4.5/4.6 Regression] ICE: in move_op_ascend, at sel-sched.c:6124 with -fselective-scheduling2

[bonzini at gnu dot org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45472

--- Comment #12 from Paolo Bonzini <bonzini at gnu dot org> 2010-10-18 17:12:59 
UTC ---
It would be nice if for

    struct a {
        char a,b,c,d;
        volatile int e;
    };

    struct a v1, v2;
    ...
    v1 = v2;

the compiler emitted only _two_ memory accesses, one for a/b/c/d and one for e.
 I'm not sure a MEM_REF(&vv1) = MEM_REF(&vv2) with volatile arguments would
achieve this.

So, even though it's just an optimization, it would be better if the IR was
designed to allow it.  Would this be the case if the front-end emitted a
volatile MODIFY_EXPR?