------- Comment #1 from carrot at google dot com 2010-08-20 03:13 -------
By simply define the following pattern
(define_insn "*thumb2_ldrd"
[(parallel [(set (match_operand:SI 0 "s_register_operand" "")
(mem:SI (match_operand:SI 2 "" "")))
(set (match_operand:SI 1 "s_register_operand" "")
(mem:SI (match_operand:SI 3 "" "")))])]
"TARGET_THUMB2 && thumb2_ldrd_addr (operands[2], operands[3])"
"*
{
rtx ldrd_addr = thumb2_ldrd_addr (operands[2], operands[3]);
operands[4] = gen_rtx_MEM (SImode, ldrd_addr);
if (ldrd_addr == operands[3])
return \"ldrd\\t%1, %0, %4\";
else
return \"ldrd\\t%0, %1, %4\";
}"
)
The combine pass can't handle it. The instructions handled by combine should
have some def-use relation. There is no such relation in this case. So another
peephole2 rule is needed to catch the opportunity.
Even though there are chances missed. After register renumbering and
instruction scheduling, more chances are revealed. Change the option -O2 to -Os
can show such an example. So a peephole rule is needed to deal with this case.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45335
