This is really a reopen of bug #41196
vshll, q3, d7, #0
is valid but the compiler and assembler choke on it and/or intrinsic. I assume
that is because the fix from #41196 tests for shifts greater than 0. However,
the zero shift is valid and needed for cheap precision expansion (i.e., vmovl).
--
Summary: ARM/NEON VSHLL instruction/intrinsic must allow shifts
by 0
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: other
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: gmcgrath at yahoo dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44658
