Compile the attached source code with options -Os -march=armv7-a -mthumb, gcc
generates:
foo4:
push {r3, r4, r5, lr}
bl bar
cmp r0, #0 // A
mov r5, r0 // B
blt .L3
...
Instructions AB can be merged into one instruction "sub r5, r0, 0"
The rtx for instructions AB are:
(insn:TI 9 7 8 src/ta.c:8 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:134 f ] [134])
(const_int 0 [0x0]))) 220 {*arm_cmpsi_insn} (expr_list:REG_DEAD
(reg:SI 0 r0 [orig:134 f ] [134])
(nil)))
(insn 8 9 10 src/ta.c:7 (set (reg/v:SI 5 r5 [orig:134 f ] [134])
(reg:SI 0 r0)) 658 {*thumb2_movsi_insn} (nil))
We have another insn pattern "*movsi_compare0" that can be used to represent
the combined operations. Should insns AB be combined automatically?
--
Summary: Move and compare with 0 can be combined
Product: gcc
Version: 4.5.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43597
