------- Comment #2 from sliao at google dot com 2010-01-07 11:31 -------
1. Yes, the flags used are "-mthumb -Os -march=armv5te".
2. For completeness, I also tried to generate 32-bit instructions. In this case
of ARM mode, GCC 4.5.0 (trunk as of last week) didn't store things onto stack
unnecessarily. I.e., there is no more "sub sp, sp, #12" instruction. See below:
00000000 <test>:
0: e92d41f0 push {r4, r5, r6, r7, r8, lr}
4: e1a05000 mov r5, r0
8: e1a04001 mov r4, r1
c: e1a07002 mov r7, r2
10: e3a06000 mov r6, #0
14: ea000009 b 40 <test+0x40>
18: e0858006 add r8, r5, r6
1c: e5980004 ldr r0, [r8, #4]
20: ebfffffe bl 0 <func>
24: e3500000 cmp r0, #0
28: e2477001 sub r7, r7, #1
2c: 0a000006 beq 4c <test+0x4c>
30: e8980003 ldm r8, {r0, r1}
34: e0843006 add r3, r4, r6
38: e8830003 stm r3, {r0, r1}
3c: e2866008 add r6, r6, #8
40: e3570000 cmp r7, #0
44: 1afffff3 bne 18 <test+0x18>
48: e3a00001 mov r0, #1
4c: e8bd41f0 pop {r4, r5, r6, r7, r8, lr}
50: e12fff1e bx lr
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42505
