Compile the attached source code with options -Os -march=armv5te -mthumb, gcc generates:
push {lr} cmp r0, #63 // A beq .L3 cmp r0, #63 // B bhi .L4 cmp r0, #45 beq .L3 cmp r0, #47 bne .L5 b .L3 .L4: cmp r0, #99 bne .L5 .L3: mov r0, #1 b .L2 .L5: mov r0, #0 .L2: @ sp needed for prologue pop {pc} Instruction B is the same as instruction A, and there are no other instructions between them clobber condition codes. So we can remove instruction B. -- Summary: redundant compare instruction of consecutive conditional branches Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: carrot at google dot com GCC build triplet: i686-linux GCC host triplet: i686-linux GCC target triplet: arm-eabi http://gcc.gnu.org/bugzilla/show_bug.cgi?id=41514