------- Comment #1 from tomby at gcc dot gnu dot org 2008-07-17 15:38 -------
It seems that compilation breaks this patch:
http://gcc.gnu.org/viewcvs?view=rev&revision=137201
Wrong insn is generated during splitting
(parallel [
(set (reg:TI 0 ax [orig:65 D.5521 ] [65])
(ashiftrt:TI (reg:TI 0 ax [88])
(reg:QI 2 cx [orig:66 D.5520 ] [66])))
(clobber (reg:CC 17 flags)) ])
in ix86_split_ashr by calling
emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2])).
Problem is that low[0] and high[0] are in DI mode and x86_shift_adj_3 accepts
only operands in SI mode.
--
tomby at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ubizjak at gmail dot com
Status|UNCONFIRMED |NEW
Ever Confirmed|0 |1
Last reconfirmed|0000-00-00 00:00:00 |2008-07-17 15:38:27
date| |
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36786
