[Bug rtl-optimization/36246] Reload chooses too wide mode for reg->mem->reg reload

[ubizjak at gmail dot com]

------- Comment #1 from ubizjak at gmail dot com  2008-05-16 06:42 -------
32bit targets (-mregparm=3) choose 32bit moves:

Reloads for insn # 9
Reload 0: reload_in (SI) = (reg/v:SI 1 dx [orig:60 __q2 ] [60])
        reload_out (V2SI) = (reg:V2SI 22 xmm1 [65])
        SSE_REGS, RELOAD_OTHER (opnum = 0)
        reload_in_reg: (reg/v:SI 1 dx [orig:60 __q2 ] [60])
        reload_out_reg: (reg:V2SI 22 xmm1 [65])
        reload_reg_rtx: (reg:V2SI 21 xmm0)
Reload 1: reload_in (SI) = (reg/v:SI 0 ax [orig:59 __q3 ] [59])
        SSE_REGS, RELOAD_FOR_INPUT (opnum = 2)
        reload_in_reg: (reg/v:SI 0 ax [orig:59 __q3 ] [59])
        reload_reg_rtx: (reg:SI 23 xmm2)

This results in:

(insn 28 6 29 2 uuu.c:7 (set (mem/c:SI (reg/f:SI 7 sp) [0 S4 A8])
        (reg/v:SI 1 dx [orig:60 __q2 ] [60])) 47 {*movsi_1} (nil))

(insn 29 28 31 2 uuu.c:7 (set (reg:SI 21 xmm0)
        (mem/c:SI (reg/f:SI 7 sp) [0 S4 A8])) 47 {*movsi_1} (nil))

(insn 31 29 32 2 uuu.c:7 (set (mem/c:SI (reg/f:SI 7 sp) [0 S4 A8])
        (reg/v:SI 0 ax [orig:59 __q3 ] [59])) 47 {*movsi_1} (nil))

(insn 32 31 9 2 uuu.c:7 (set (reg:SI 23 xmm2)
        (mem/c:SI (reg/f:SI 7 sp) [0 S4 A8])) 47 {*movsi_1} (nil))

(insn:HI 9 32 30 2 uuu.c:7 (set (reg:V2SI 21 xmm0)
        (vec_concat:V2SI (reg:SI 21 xmm0)
            (reg:SI 23 xmm2))) 1338 {*vec_concatv2si_sse2} (nil))


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36246