------- Comment #3 from wilson at gcc dot gnu dot org 2008-01-11 21:23 -------
The ia64 code to insert stop bits has a built-in assumption that if we see a
register set twice in the same instruction, then we goofed, and must ICE.
The testcase has an extended asm with 3 outputs and 4 inputs. None of the
outputs are used after the asm. The register allocator decided to assign two
of the outputs to the same hard register which is OK if they are never used.
But they are used inside the asm, so this won't work. If I mark the outputs as
early clobber, i.e. change
: "=r" (compare_value) ,
"=r" (exchange_value) ,
"=r" (sum)
to
: "=&r" (compare_value) ,
"=&r" (exchange_value) ,
"=&r" (sum)
Then there is no ICE, and I also get correct code.
So we need to fix the asm at a minimum. It doesn't appear to be from gcc code.
We might also need to fix the ia64 backend to allow the same reg to be written
twice by the same insn, since it can occur as this testcase shows. Though this
testcase is broken, there might be some valid way that this can occur. Maybe
just allowing this for asms is OK. Or maybe just emitting a friendlier error
message here is OK.
That was for mainline. I checked the gcc-4.1 branch, and this is the same
problem, except that all 3 outputs got assigned to the same hard register.
--
wilson at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |wilson at gcc dot gnu dot
| |org
Status|UNCONFIRMED |NEW
Ever Confirmed|0 |1
Last reconfirmed|0000-00-00 00:00:00 |2008-01-11 21:23:40
date| |
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34637
