------- Comment #16 from ubizjak at gmail dot com 2007-12-18 18:33 -------
(In reply to comment #15)
> Note two moves [(insn 36) and (insn 37)] around (insn 12).
Bah. This is the correct sequence, around (insn 10) that seems to be the root
of all problems:
(insn:HI 9 8 36 2 m.c:2 (parallel [
(set (reg:SI 2 cx [62])
(plus:SI (reg:SI 2 cx [62])
(reg:SI 0 ax [63])))
(clobber (reg:CC 17 flags))
]) 249 {*addsi_1} (nil))
(insn 36 9 10 2 m.c:2 (set (reg:SI 0 ax)
(reg:SI 4 si [orig:66 b ] [66])) 47 {*movsi_1} (nil))
(insn:HI 10 36 37 2 m.c:2 (parallel [
(set (reg:DI 0 ax)
(mult:DI (zero_extend:DI (reg:SI 0 ax))
(zero_extend:DI (reg:SI 3 bx [orig:64 a ] [64]))))
(clobber (reg:CC 17 flags))
]) 304 {*umulsidi3_insn} (nil))
(insn 37 10 11 2 m.c:2 (set (reg:DI 3 bx [61])
(reg:DI 0 ax)) 88 {*movdi_2} (nil))
DImode AX as found in (insn 10) could simply be propagated up and down RTL
stream as SImode destination of (insn 8) and SImode source of (insn 12). For
some reason, RA is afraid to allocate registers in mixed modes.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17236
