------- Comment #3 from pinskia at gcc dot gnu dot org 2007-07-26 17:02 -------
(In reply to comment #2)
> (In reply to comment #2)
> Just want a clarification:
> I see you're compiling on PPU (since you're using -maltivec).
> Does this problematic also on SPU?
No because extraction from a vector is a simple rotate.
> Does SPU has this LHS hazard?
No because there is no store queue on the SPU.
>
> Another question:
> lwz r0,-20(r1) <---- LHS hazard
> stw r0,lo16(_e)(r2)
>
> The problem here is these 2 insns, right?
No, it is the load after the store to the same address:
stvewx v1,0,r2
lwz r0,-20(r1) <---- LHS hazard
r2 at this point is equal to -20(r1).
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32826
