With gcc 4.0.x, left bitshift on 128-bit TIMode doesn't seem to be working
properly. For example, using the attached code and compiled under 4.0.4, I
initialize a 128-bit TIMode variable called "mask" to 1U, left-shift it by the
entered number of bits and compute 0U-mask, while printing the contents of that
128-bit variable in hex at each step.
The code compiled with gcc 4.0.4 produced the following:
./test_128_404
Enter the number of bits for left shift: 8
mask initialized to 1U: 0000000000000000 0000000000000001
After the left shift by 8 bits: 0000000000000100 0000000000000000
0U-mask=ffffffffffffff00 0000000000000000
On the very same box compiled with gcc 3.4.6:
./test_128_346
Enter the number of bits for left shift: 8
mask initialized to 1U: 0000000000000000 0000000000000001
After the left shift by 8 bits: 0000000000000000 0000000000000100
0U-mask=ffffffffffffffff ffffffffffffff00
Compiling under gcc 4.1.1 gets the same results as 3.4.6, i.e., it appears that
only 4.0.x compilers are broken.
This is 100% reproducible - I got identical results on several different boxes
with different variants of Fedora/CentOS and gcc 4.0.2 and 4.0.4, all AMD boxes
though. For the record, here is my OS data:
uname -a
Linux Centos4.roundbox.com 2.6.9-42.0.3.ELsmp #1 SMP Fri Oct 6 06:28:26 CDT
2006 x86_64 x86_64 x86_64 GNU/Linux
cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 35
model name : Dual Core AMD Opteron(tm) Processor 175
stepping : 2
cpu MHz : 1809.293
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext lm 3dnowext 3
dnow pni
bogomips : 3622.46
TLB size : 1088 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 35
model name : Dual Core AMD Opteron(tm) Processor 175
stepping : 2
cpu MHz : 1809.293
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext lm 3dnowext 3
dnow pni
bogomips : 3622.46
TLB size : 1088 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
--
Summary: left bitshift is broken with 128-bit TIMode
Product: gcc
Version: 4.0.4
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c++
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: igor at roundbox dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32025
