I build a new target for experiment, and my GCC version is 4.1.1
I have one question
at combine pass , if
(set ( reg 1)
(and (reg 2)
(const_int 0x80000001)))
(cmp (reg1 )(const_0)
if compare code is GE or LT
and src2 is zero
the const_int will be 0x80000000
because it just need significant bit
but
if reg 1 will be used by following insns
the const_int shouldn't be modified.
following message are -daP result
"at insn 13 that is my problem"
-JASON-
--life pass
;; Function foo (foo)
120 registers.
Register 107 used 4 times across 6 insns; set 3 times.
Register 109 used 2 times across 2 insns in block 0; set 1 time; pointer.
Register 111 used 2 times across 2 insns in block 0; set 1 time.
Register 112 used 9 times across 11 insns; set 4 times.
Register 113 used 2 times across 2 insns in block 0; set 1 time.
Register 115 used 11 times across 17 insns; set 4 times.
Register 116 used 2 times across 2 insns in block 2; set 1 time.
Register 117 used 2 times across 2 insns in block 4; set 1 time.
Register 118 used 2 times across 2 insns in block 5; set 1 time.
10 basic blocks, 15 edges.
Basic block 0 prev -1, next 1, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: ENTRY [100.0%] (fallthru)
Successors: 2 [50.0%] 1 [50.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
Basic block 1 prev 0, next 2, loop_depth 0, count 0, freq 5000, maybe hot.
Predecessors: 0 [50.0%] (fallthru)
Successors: 2 [100.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
Basic block 2 prev 1, next 3, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: 0 [50.0%] 1 [100.0%] (fallthru)
Successors: 4 [50.0%] 3 [50.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Basic block 3 prev 2, next 4, loop_depth 0, count 0, freq 5000, maybe hot.
Predecessors: 2 [50.0%] (fallthru)
Successors: 4 [100.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Basic block 4 prev 3, next 5, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: 2 [50.0%] 3 [100.0%] (fallthru)
Successors: 8 [29.0%] 5 [71.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Basic block 5 prev 4, next 6, loop_depth 0, count 0, freq 7100, maybe hot.
Predecessors: 4 [71.0%] (fallthru)
Successors: 7 [71.0%] 6 [29.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Basic block 6 prev 5, next 7, loop_depth 0, count 0, freq 2059, maybe hot.
Predecessors: 5 [29.0%] (fallthru)
Successors: 9 [100.0%]
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
Basic block 7 prev 6, next 8, loop_depth 0, count 0, freq 5041, maybe hot.
Predecessors: 5 [71.0%]
Successors: 9 [100.0%]
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
Basic block 8 prev 7, next 9, loop_depth 0, count 0, freq 2900, maybe hot.
Predecessors: 4 [29.0%]
Successors: 9 [100.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
Registers live at end: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
Basic block 9 prev 8, next -2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: 8 [100.0%] (fallthru) 6 [100.0%] 7 [100.0%]
Successors: EXIT [100.0%] (fallthru)
Registers live at start: 12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
Registers live at end: 0 [r0] 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
try_optimize_cfg iteration 1
(note 2 0 6 NOTE_INSN_DELETED)
(note 6 2 9 NOTE_INSN_FUNCTION_BEG)
;; Start of basic block 0, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(note 9 6 11 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 11 9 12 0 (set (reg/f:SI 109)
(symbol_ref:SI ("a") [flags 0x2] <var_decl 0xb7dba0b0 a>)) 68
{*movsi_var} (nil)
(nil))
(insn 12 11 13 0 (set (reg:SI 111 [ a ])
(mem/c/i:SI (reg/f:SI 109) [0 a+0 S4 A32])) 70 {*movsi}
(insn_list:REG_DEP_TRUE 11 (nil))
(expr_list:REG_DEAD (reg/f:SI 109)
(nil)))
(insn 13 12 14 0 (set (reg:SI 112)
(and:SI (reg:SI 111 [ a ])
(const_int -2147483647 [0x80000001]))) 124 {andsi3}
(insn_list:REG_DEP_TRUE 12 (nil))
(expr_list:REG_DEAD (reg:SI 111 [ a ])
(nil)))
(insn 14 13 15 0 (set (reg:SI 113)
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
(insn 15 14 16 0 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 112)
(reg:SI 113))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 13
(insn_list:REG_DEP_TRUE 14 (nil)))
(expr_list:REG_DEAD (reg:SI 113)
(nil)))
(jump_insn 16 15 66 0 (set (pc)
(if_then_else (ge (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 20)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 15 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil))))
;; End of basic block 0, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
;; Start of basic block 1, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
112
(note 66 16 17 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn 17 66 18 1 (set (reg:SI 112)
(plus:SI (reg:SI 112)
(const_int -1 [0xffffffff]))) 97 {*addsi3} (nil)
(nil))
(insn 18 17 19 1 (set (reg:SI 112)
(ior:SI (reg:SI 112)
(const_int -2 [0xfffffffe]))) 125 {iorsi3} (insn_list:REG_DEP_TRUE
17 (nil))
(nil))
(insn 19 18 20 1 (set (reg:SI 112)
(plus:SI (reg:SI 112)
(const_int 1 [0x1]))) 97 {*addsi3} (insn_list:REG_DEP_TRUE 18
(nil))
(nil))
;; End of basic block 1, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
;; Start of basic block 2, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
112
(code_label 20 19 67 2 5 "" [1 uses])
(note 67 20 21 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 21 67 22 2 (set (reg:SI 115)
(and:SI (reg:SI 112)
(const_int -2147483647 [0x80000001]))) 124 {andsi3} (nil)
(expr_list:REG_DEAD (reg:SI 112)
(nil)))
(insn 22 21 23 2 (set (reg:SI 116)
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
(insn 23 22 24 2 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 115)
(reg:SI 116))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 21
(insn_list:REG_DEP_TRUE 22 (nil)))
(expr_list:REG_DEAD (reg:SI 116)
(nil)))
(jump_insn 24 23 68 2 (set (pc)
(if_then_else (ge (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 28)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 23 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil))))
;; End of basic block 2, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 3, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 68 24 25 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 25 68 26 3 (set (reg:SI 115)
(plus:SI (reg:SI 115)
(const_int -1 [0xffffffff]))) 97 {*addsi3} (nil)
(nil))
(insn 26 25 27 3 (set (reg:SI 115)
(ior:SI (reg:SI 115)
(const_int -2 [0xfffffffe]))) 125 {iorsi3} (insn_list:REG_DEP_TRUE
25 (nil))
(nil))
(insn 27 26 28 3 (set (reg:SI 115)
(plus:SI (reg:SI 115)
(const_int 1 [0x1]))) 97 {*addsi3} (insn_list:REG_DEP_TRUE 26
(nil))
(nil))
;; End of basic block 3, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 4, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(code_label 28 27 69 4 6 "" [1 uses])
(note 69 28 29 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 29 69 30 4 (set (reg:SI 117)
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
(insn 30 29 31 4 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 115)
(reg:SI 117))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 29
(nil))
(expr_list:REG_DEAD (reg:SI 117)
(nil)))
(jump_insn 31 30 70 4 (set (pc)
(if_then_else (eq (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 47)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 30 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 2900 [0xb54])
(nil))))
;; End of basic block 4, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 5, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 70 31 32 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 32 70 33 5 (set (reg:SI 118)
(const_int 1 [0x1])) 69 {*movsi_const} (nil)
(nil))
(insn 33 32 34 5 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 115)
(reg:SI 118))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 32
(nil))
(expr_list:REG_DEAD (reg:SI 118)
(nil)))
(jump_insn 34 33 38 5 (set (pc)
(if_then_else (ne (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref:SI 42)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 33 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil))))
;; End of basic block 5, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 6, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 38 34 39 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 39 38 74 6 (set (reg:SI 107 [ D.1201 ])
(reg:SI 115)) 70 {*movsi} (nil)
(expr_list:REG_DEAD (reg:SI 115)
(expr_list:REG_EQUAL (const_int 1 [0x1])
(nil))))
(jump_insn 74 39 75 6 (set (pc)
(label_ref 50)) -1 (nil)
(nil))
;; End of basic block 6, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
(barrier 75 74 42)
;; Start of basic block 7, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(code_label 42 75 43 7 2 "" [1 uses])
(note 43 42 44 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 44 43 76 7 (set (reg:SI 107 [ D.1201 ])
(const_int -1 [0xffffffff])) 69 {*movsi_const} (nil)
(nil))
(jump_insn 76 44 77 7 (set (pc)
(label_ref 50)) -1 (nil)
(nil))
;; End of basic block 7, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
(barrier 77 76 47)
;; Start of basic block 8, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(code_label 47 77 48 8 3 "" [1 uses])
(note 48 47 49 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 49 48 50 8 (set (reg:SI 107 [ D.1201 ])
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
;; End of basic block 8, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
;; Start of basic block 9, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
107
(code_label 50 49 51 9 7 "" [2 uses])
(note 51 50 55 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(note 55 51 58 9 NOTE_INSN_FUNCTION_END)
(insn 58 55 64 9 (set (reg/i:SI 0 r0 [ <result> ])
(reg:SI 107 [ D.1201 ])) 70 {*movsi} (nil)
(expr_list:REG_DEAD (reg:SI 107 [ D.1201 ])
(nil)))
(insn 64 58 0 9 (use (reg/i:SI 0 r0 [ <result> ])) -1 (insn_list:REG_DEP_TRUE
58 (nil))
(nil))
;; End of basic block 9, registers live:
0 [r0] 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
--combine pass
;; Function foo (foo)
insn_cost 11: 12
insn_cost 12: 4
insn_cost 13: 4
insn_cost 14: 4
insn_cost 15: 4
insn_cost 16: 0
insn_cost 17: 4
insn_cost 18: 4
insn_cost 19: 4
insn_cost 21: 4
insn_cost 22: 4
insn_cost 23: 4
insn_cost 24: 0
insn_cost 25: 4
insn_cost 26: 4
insn_cost 27: 4
insn_cost 29: 4
insn_cost 30: 4
insn_cost 31: 0
insn_cost 32: 4
insn_cost 33: 4
insn_cost 34: 0
insn_cost 39: 4
insn_cost 74: 0
insn_cost 44: 4
insn_cost 76: 0
insn_cost 49: 4
insn_cost 58: 4
insn_cost 64: 0
rejecting combination of insns 14 and 15
original costs 4 + 4 = 8
replacement cost 12
rejecting combination of insns 22 and 23
original costs 4 + 4 = 8
replacement cost 12
rejecting combination of insns 29 and 30
original costs 4 + 4 = 8
replacement cost 12
rejecting combination of insns 32 and 33
original costs 4 + 4 = 8
replacement cost 12
(note 2 0 6 NOTE_INSN_DELETED)
(note 6 2 9 NOTE_INSN_FUNCTION_BEG)
;; Start of basic block 0, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(note 9 6 11 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 11 9 12 0 (set (reg/f:SI 109)
(symbol_ref:SI ("a") [flags 0x2] <var_decl 0xb7dba0b0 a>)) 68
{*movsi_var} (nil)
(nil))
(insn 12 11 13 0 (set (reg:SI 111 [ a ])
(mem/c/i:SI (reg/f:SI 109) [0 a+0 S4 A32])) 70 {*movsi}
(insn_list:REG_DEP_TRUE 11 (nil))
(expr_list:REG_DEAD (reg/f:SI 109)
(nil)))
(note 13 12 14 0 NOTE_INSN_DELETED)
(insn 14 13 15 0 (set (reg:SI 112)
(and:SI (reg:SI 111 [ a ])
(const_int -2147483648 [0x80000000]))) 124 {andsi3}
(insn_list:REG_DEP_TRUE 12 (nil))
(nil))
(insn 15 14 16 0 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 111 [ a ])
(const_int 0 [0x0]))) 147 {*unicore_cmpsi_insn} (nil)
(expr_list:REG_DEAD (reg:SI 111 [ a ])
(nil)))
(jump_insn 16 15 66 0 (set (pc)
(if_then_else (ge (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 20)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 15 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil))))
;; End of basic block 0, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
;; Start of basic block 1, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
112
(note 66 16 17 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn 17 66 18 1 (set (reg:SI 112)
(plus:SI (reg:SI 112)
(const_int -1 [0xffffffff]))) 97 {*addsi3} (nil)
(nil))
(insn 18 17 19 1 (set (reg:SI 112)
(ior:SI (reg:SI 112)
(const_int -2 [0xfffffffe]))) 125 {iorsi3} (insn_list:REG_DEP_TRUE
17 (nil))
(nil))
(insn 19 18 20 1 (set (reg:SI 112)
(plus:SI (reg:SI 112)
(const_int 1 [0x1]))) 97 {*addsi3} (insn_list:REG_DEP_TRUE 18
(nil))
(nil))
;; End of basic block 1, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 112
;; Start of basic block 2, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
112
(code_label 20 19 67 2 5 "" [1 uses])
(note 67 20 21 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 21 67 22 2 NOTE_INSN_DELETED)
(insn 22 21 23 2 (set (reg:SI 115)
(and:SI (reg:SI 112)
(const_int -2147483648 [0x80000000]))) 124 {andsi3} (nil)
(nil))
(insn 23 22 24 2 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 112)
(const_int 0 [0x0]))) 147 {*unicore_cmpsi_insn} (nil)
(expr_list:REG_DEAD (reg:SI 112)
(nil)))
(jump_insn 24 23 68 2 (set (pc)
(if_then_else (ge (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 28)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 23 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil))))
;; End of basic block 2, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 3, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 68 24 25 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 25 68 26 3 (set (reg:SI 115)
(plus:SI (reg:SI 115)
(const_int -1 [0xffffffff]))) 97 {*addsi3} (nil)
(nil))
(insn 26 25 27 3 (set (reg:SI 115)
(ior:SI (reg:SI 115)
(const_int -2 [0xfffffffe]))) 125 {iorsi3} (insn_list:REG_DEP_TRUE
25 (nil))
(nil))
(insn 27 26 28 3 (set (reg:SI 115)
(plus:SI (reg:SI 115)
(const_int 1 [0x1]))) 97 {*addsi3} (insn_list:REG_DEP_TRUE 26
(nil))
(nil))
;; End of basic block 3, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 4, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(code_label 28 27 69 4 6 "" [1 uses])
(note 69 28 29 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 29 69 30 4 (set (reg:SI 117)
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
(insn 30 29 31 4 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 115)
(reg:SI 117))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 29
(nil))
(expr_list:REG_DEAD (reg:SI 117)
(nil)))
(jump_insn 31 30 70 4 (set (pc)
(if_then_else (eq (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref 47)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 30 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 2900 [0xb54])
(nil))))
;; End of basic block 4, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 5, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 70 31 32 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 32 70 33 5 (set (reg:SI 118)
(const_int 1 [0x1])) 69 {*movsi_const} (nil)
(nil))
(insn 33 32 34 5 (set (reg:CC 97 r0cc)
(compare:CC (reg:SI 115)
(reg:SI 118))) 147 {*unicore_cmpsi_insn} (insn_list:REG_DEP_TRUE 32
(nil))
(expr_list:REG_DEAD (reg:SI 118)
(nil)))
(jump_insn 34 33 38 5 (set (pc)
(if_then_else (ne (reg:CC 97 r0cc)
(const_int 0 [0x0]))
(label_ref:SI 42)
(pc))) 148 {*unicore_cond_branch} (insn_list:REG_DEP_TRUE 33 (nil))
(expr_list:REG_DEAD (reg:CC 97 r0cc)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil))))
;; End of basic block 5, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 115
;; Start of basic block 6, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
115
(note 38 34 39 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 39 38 74 6 (set (reg:SI 107 [ D.1201 ])
(reg:SI 115)) 70 {*movsi} (nil)
(expr_list:REG_DEAD (reg:SI 115)
(expr_list:REG_EQUAL (const_int 1 [0x1])
(nil))))
(jump_insn 74 39 75 6 (set (pc)
(label_ref 50)) -1 (nil)
(nil))
;; End of basic block 6, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
(barrier 75 74 42)
;; Start of basic block 7, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(code_label 42 75 43 7 2 "" [1 uses])
(note 43 42 44 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 44 43 76 7 (set (reg:SI 107 [ D.1201 ])
(const_int -1 [0xffffffff])) 69 {*movsi_const} (nil)
(nil))
(jump_insn 76 44 77 7 (set (pc)
(label_ref 50)) -1 (nil)
(nil))
;; End of basic block 7, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
(barrier 77 76 47)
;; Start of basic block 8, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
(code_label 47 77 48 8 3 "" [1 uses])
(note 48 47 49 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 49 48 50 8 (set (reg:SI 107 [ D.1201 ])
(const_int 0 [0x0])) 69 {*movsi_const} (nil)
(nil))
;; End of basic block 8, registers live:
12 [fp] 14 [sp] 98 [sfp] 99 [afp] 107
;; Start of basic block 9, registers live: 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
107
(code_label 50 49 51 9 7 "" [2 uses])
(note 51 50 55 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(note 55 51 58 9 NOTE_INSN_FUNCTION_END)
(insn 58 55 64 9 (set (reg/i:SI 0 r0 [ <result> ])
(reg:SI 107 [ D.1201 ])) 70 {*movsi} (nil)
(expr_list:REG_DEAD (reg:SI 107 [ D.1201 ])
(nil)))
(insn 64 58 0 9 (use (reg/i:SI 0 r0 [ <result> ])) -1 (insn_list:REG_DEP_TRUE
58 (nil))
(nil))
;; End of basic block 9, registers live:
0 [r0] 12 [fp] 14 [sp] 98 [sfp] 99 [afp]
--
Summary: error at combine pass
Product: gcc
Version: 4.1.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: hth94 at cs dot ccu dot edu dot tw
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30163
