This code sample generates incorrect code on 64 bit SPARC when compiled -O2
-mvis -mcpu=ultrasparc.
typedef short v16_2_t __attribute__((vector_size(4)));
void vis_mul_block(const v16_2_t * __restrict in1,
const v16_2_t * __restrict in2,
v16_2_t * __restrict out)
{
/* assumes caller set GSR */
out[0] = __builtin_vis_fpackfix(__builtin_vis_fmuld8ulx16(in1[0], in2[0]));
out[1] = __builtin_vis_fpackfix(__builtin_vis_fmuld8ulx16(in1[1], in2[1]));
}
The function body is
ld [%o0+4], %f9
ld [%o1+4], %f11
ld [%o0], %f8
fmuld8ulx16 %f9, %f11, %f9
fmuld8ulx16 %f8, %f10, %f8
fpackfix %f9, %f9
fpackfix %f8, %f8
st %f9, [%o2+4]
jmp %o7+8
st %f8, [%o2]
The compiler does not realize that 64 bit floating point registers are even+odd
pairs of 32 bit floating point registers when the register number is less than
32. Odd numbered 32 bit registers can not be used as 64 bit output registers,
such as the output of fmuld8ulx16.
Perhaps the definition of HARD_REGNO_MODE_OK or HARD_REGNO_NREGS needs revision
for vector-integer types.
--
Summary: SPARC V9 uses bad FP register for VIS instructions
Product: gcc
Version: 4.1.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: jfc at mit dot edu
GCC build triplet: sparc64-sun-solaris2.9
GCC host triplet: sparc64-sun-solaris2.9
GCC target triplet: sparc64-sun-solaris2.9
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29314
