------- Comment #4 from ramon dot garcia dot f+gcc at gmail dot com 2006-05-11 23:42 ------- Sorry, this bug was based on a misunderstanding.
I was playing with some integer SSE on an Athlon and got surprised because it seemed to work, that is, no ill instruction fault. From Googling one finds pages about AMD Athlon supporting integer SSE. But with GDB one sees the xmm registers didn't seem to be affected. Some promotional materials of AMD mention compatibility with Intel's integer SSE http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_756_3734%5E3738,00.html What was happening? The AMD processors "reinterpret" integer SSE instructions and map them to "equivalent" MMX instructions!!! So they "sort of" work, but restricted to 64 bits and using MMX registers. Sorry for wasting your time, and for the tone of the bug report. Here is an assembly program: .data a: .word 100, 200, 300, 400, 500, 600, 700, 800 b: .word 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000 c: .fill 8, 2, 0 .text .globl main main: push %ebp mov %esp,%ebp movdqa a,%xmm0 movdqa b,%xmm1 paddw %xmm1,%xmm0 movdqa %xmm0,c mov $8,%ecx 1: movzwl (c-2)(%ecx,%ecx,1),%eax pushl %eax loop 1b .section .rodata 2: .asciz "%d %d %d %d %d %d %d %d\n" .text pushl $2b call printf mov $0,%eax leave ret that produces the correct output on a Pentium IV: 1100 2200 3300 4400 5500 6600 7700 8800 but only the first four numbers are added in an AMD Athlon: 1100 2200 3300 4400 0 0 0 0 By the way, the texinfo documentation of GCC builtin functions http://gcc.gnu.org/onlinedocs/gcc-4.1.0/gcc/X86-Built_002din-Functions.html#X86-Built_002din-Functions seems to need a review. I think that there is a typo, -msse is mentioned twice and there is no mention about special intrinsic functions with -msse2. Ramon -- ramon dot garcia dot f+gcc at gmail dot com changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |RESOLVED Resolution| |INVALID http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27562
