Cool. You should use "$(CC)" instead of "gcc" explicitly. Read the "implicit
variables" section in the GNU manual regarding what built-in variables are
there. Ideally you should use "$(LINK_CMD)" there too. That is defined towards
the top of the Makefile.
Good you have found "echo". You know you can "echo $(CC)" etc to display what
values those variables take, too?
The first rule likewise should be "$(COMPILE)" to fit in to the rest, in terms
of style.
Certainly very well done snd congratulations you have found your way around
libtool and make!
On Friday, 14 July 2023 at 14:26:28 BST, Ahmet Göksu <[email protected]>
wrote:
Thanks a lot, it works now.
I have updated the makefile like:
# Build ftbench.o
$(FTBENCH_OBJ): $(FTBENCH_SRC)
@echo "Building ftbench object..." $(CC) $(INCLUDES) -c $< -o $@
# Build ftbench
$(FTBENCH_BIN): $(FTBENCH_OBJ)
@echo "Linking ftbench..." $(LIBTOOL) --mode=link gcc -L$(LIB_DIR) -lfreetype
$< -o $@ @echo "Built."
but at the second rule, to produce this line: $(LIBTOOL) --mode=link gcc, i
used gcc instead of $(CC) which is an also a libtool. Is it a wrong approach? i
remember something about not to using gcc in past mails.
Best,Goksugoksu.inOn 12 Jul 2023 22:17 +0300, Hin-Tak Leung
<[email protected]>, wrote:
(Please keep the CC to freetype-devel)
libtool is also heavily in the GNU family, although mainly maintained by the
people at https://sourceware.org/ , I think. (ancient time people politics...)
. http://www.gnu.org/software/libtool/ is also quite well-maintained.
You actually don't need to know much about libtool, really; it mostly just
launches other commands. i.e.
what follows " libtool —mode=compile .... " is mostly a valid compiler command,
you should be able to cut and paste it and run it directly. If it does not
work, variable expansions inside your makefile is wrong.
So what follows --mode=compile should mostly looks like
gcc source1.c -o source1.o
or something similar.
The "libtool —mode=link .... " mode is mostly a linker command too. So it
should looks like
gcc -Llocation1 -Llocation2 -lone -ltwo -Iinclude1 -Iinclude2 1source1.o
source2.o source3.o -o binary1
The only difference from a properly valid linking command vs what follows
"libtool —mode=link .... " is that some *.la files happens instead of the
equivalent *.so or *.a . For example, I am doing ft2-demo builds at the moment,
and the screen echos this commands it is running:
libtool --mode=link ... /home/Hin-Tak/git-others/freetype2/objs/libfreetype.la
...
in the middle. and it is followed by this information in the next line:
libtool: link: ... /home/Hin-Tak/git-others/freetype2/objs/.libs/libfreetype.so
...
What follows "libtool: link: " is the actual compiler command it is running.
That you should be able to cut and paste and run directly and it should execute
without error.
Anyway, this is just a quick tutorial... there is no substitute for actually
reading the manual :-). They are quite well written, as I keep saying :-).
Your "libtool --mode=link .... " line below is obviously wrong. It is missing
the actual compiler name (gcc/cc/clang) itself.
On Wednesday, 12 July 2023 at 16:22:04 BST, Ahmet Göksu <[email protected]> wrote:
thanks a lot, Make works good actually :)
the problem i am facing is linking the .o file to binary (even by terminal
commands, manually).
like:
libtool —mode=link ftbench.o -o ftbench
some binary, flag or parameter needed i think.
Thanks,
Goksu
goksu.in
On 12 Jul 2023 6:12 PM +0300, Hin-Tak Leung <[email protected]>,
wrote:
The GNU Make manual is quite useful - and very well-written too. Go and
download it and sit down for an afternoon, away from the keyboard, read
sections of it. Good indexes and cross-references too.
I think you probably want to do "make -n", for make to just print out what it
will do, and just read what all the variables expanding to. It is really just
Goal : dependencies
How-to-make-goal-from-dependencies
There is a section on implicit variables ($@, $^, $<, $CC) and patterns and
substitutions, (usage of subst).
As I said, it is very well written, and explains a lot of things much better
than I or anybody could ever do in a short e-mail :-).
On Wednesday, 12 July 2023 at 22:58:47 GMT+8, Ahmet Göksu <[email protected]>
wrote:
actually i am stucked in linking. cc generates object file well but here i am
missing something:
$(LIBTOOL) --mode=link $(CC) $(subst /,$(f),$(LDFLAGS)) $^ -o $@ $(subst
/,$(f),$(FTLIB) $(EFENCE))
tried also this
$(LIBTOOL) --mode=link $(CC) $^ -o $@ $(subst /,$(f),$(FTLIB) $(EFENCE))
and this
$(LIBTOOL) --mode=link $(CC) $^ -o $@
Best,
Goksu
goksu.in
On 12 Jul 2023 5:33 PM +0300, Hin-Tak Leung <[email protected]>,
wrote:
On Wednesday, 12 July 2023 at 21:25:05 GMT+8, Ahmet Göksu <[email protected]>
wrote:
> but i am stucked to binary.
$(FTBENCH_BIN): $(OBJ_DIR)/ftbench.$(SO)
$(LIBTOOL) --mode=link $(CC) $(subst /,$(f),$(LDFLAGS)) $^ -o $@ $(subst
/,$(f),$(FTLIB) $(EFENCE))
> i am trying to do it same way in the demos, yet didnt figured it out.
I haven't been following your work at all, so I could be wrong. I think you
want to modify the first of the above line to:
$(OBJ_DIR)/$(FTBENCH_BIN): $(OBJ_DIR)/ftbench.$(SO)
...
And elsewhere in the makefile, there should be a pseudo-target of the form:
all : binary1 binary2 binary3 binary4
(in multiple lines continued and separated by "\")
You want to change that to this sort of pattern too:
all : $(OBJ_DIR)/binary1 ...
