On Wed, Mar 19, 2025 at 10:44:00AM -0400, Connor Abbott wrote:
> This will be used by drm/msm for GPU page faults, replacing the manual
> register reading it does.
>
> Signed-off-by: Connor Abbott <[email protected]>
> Reviewed-by: Rob Clark <[email protected]>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 6 ++--
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 35
> ++++++++++++++----------
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 7 +++--
> 3 files changed, 29 insertions(+), 19 deletions(-)
[...]
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index
> ade4684c14c9b2724a71e2457288dbfaf7562c83..a02078eb968b81a35c1c086ed7007ea2a453ef94
> 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -405,13 +405,20 @@ static const struct iommu_flush_ops
> arm_smmu_s2_tlb_ops_v1 = {
> };
>
>
> -void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> +void arm_smmu_read_context_fault_info(struct arm_smmu_domain *smmu_domain,
> struct arm_smmu_context_fault_info *cfi)
> {
> + struct arm_smmu_device *smmu = smmu_domain->smmu;
> + int idx = smmu_domain->cfg.cbndx;
> +
> cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> + cfi->ttbr0 = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_TTBR0);
> cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> + cfi->fsynr0 = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> + cfi->fsynr1 = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR1);
> cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)
> + cfi->contextidr = arm_smmu_cb_read(smmu, idx,
> ARM_SMMU_CB_CONTEXTIDR);
I think this leaves 'cfi->contextidr' uninitialised for stage-2 domains.
We should probably either zero it here or just zero-initialise the whole
'cfi' struct in arm_smmu_context_fault() with a:
struct arm_smmu_context_fault_info cfi = {};
line.
Will
