On Fri, 2 Sept 2022 at 12:35, Kalyan Thota <[email protected]> wrote:
>
>
>
> >-----Original Message-----
> >From: Dmitry Baryshkov <[email protected]>
> >Sent: Friday, August 26, 2022 5:02 PM
> >To: Kalyan Thota <[email protected]>; Kalyan Thota (QUIC)
> ><[email protected]>; [email protected]
> >Cc: [email protected]; [email protected];
> >[email protected]; [email protected]; linux-
> >[email protected]; [email protected]; [email protected]; Vinod
> >Polimera (QUIC) <[email protected]>; Abhinav Kumar (QUIC)
> ><[email protected]>
> >Subject: Re: [v1] drm/msm/disp/dpu1: add support for hierarchical flush for
> >dspp
> >in sc7280
Ugh. I'd kindly ask to fix your email client to behave like a normal one.
> >>>> @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> >>>> ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> >>>> ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
> >>>> ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
> >>>> - ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
> >>>> + if (cap & BIT(DPU_CTL_HIERARCHICAL_FLUSH)) {
> >>>> + ops->get_bitmask_dspp =
> >>>> + dpu_hw_ctl_get_bitmask_dspp_v1;
> >>>
> >>> We have used _v1 for active CTLs. What is the relationship between
> >>> CTL_HIERARCHILCAL_FLUSH and active CTLs?
> >> Active CTL design replaces legacy CTL_MEM_SEL, CTL_OUT_SEL registers
> >> in grouping the resources such as WB, INTF, pingpong, DSC etc into the
> >> data path DSPP hierarchical flush will gives us a finer control on which
> >> post
> >processing blocks to be flushed as part of the composition ( like IGC, PCC,
> >GC ..
> >etc ) These blocks are contained in DSPP package.
> >
> >So, I assume that hierarchical DSPP flush does not exist on non-active CTL
> >SoCs.
> >Which supported SoCs do support the hierarchichal DSPP flush?
> >
> Dspp Sub-block flush is supported from the DPU 7-series, the only target in
> the catalogue is sc7280.
Ack, thanks.
--
With best wishes
Dmitry
