At 11:56 PM 5/6/2005 +0200, tom ehlert wrote:
>> > The optimization is the one that tries to align EDI to an >> > eight-byte boundary before the main REP MOVSD.
Allow me to have a different 'opinion'. As far as I understand+remember Intel optimization guides (whatever CPU that was for), alignment of ESI is more important.
Table 19.5, Data Misalignment Penalty for REP MOVSD, in "Pentium Processor Optimization Tools" by Michael Schmit (to pull out an obscure reference) agrees with you for 386sx, 386, 486. Aligning to [E]SI provides a smaller penalty when [E]SI is aligned and [E]DI is not than the reverse. Pentium is the reverse: you should align to EDI since it provides no penalty. CPUs above that, the book is too old. Nothing else handy seems to say much on the subject.
But for my purposes, my comments in the post could easily exchange ESI for EDI as far as the cache line optimization and 8-byte boundaries. I wasn't making about point about EDI alignment specifically, but about data (both ESI and EDI) alignments taken to the cache line boundary, aka using "burst read/write access". We're looking for the 3x speed-up on REP MOVSD with Pentium Pro, II, and III, if possible. Within the discussion, everything else is a side optimization to that goal.
However, with a 386sx through 486, you are correct: 4-byte boundary alignment for either ESI or EDI improves throughput compared to both misaligned, but alignment to ESI enjoys a smaller performance penalty. Pentium goes the other way. Aligned EDI gives a 0% penalty with misaligned ESI. Still, you generally optimize for the slowest expected machine in common use, so perhaps you're better off with ESI alignment.
Or maybe the table is wrong for Pentium. Exact answers on the subject are hard to track down. Books have been written on the subject (obviously).
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