Hi!
> "inp()" and 0x40:0x6c are both CPU-heavy; isn't there some nicier=20
> method???
You can "HLT" between every two 40[6c] readouts - if you know that there
is no "CLI" state. However, why is it a problem to have CPU-heavy beep?
For example boot menu delay in kernel does not "HLT" either and nobody
except me ever mentioned the "HLT" energy saving possibility there.
> There was also the suggestion to hook INT-1C.
Possible but 40[6c] is more or less equivalent anyway.
> Actually, I wonder, I dimmly remember some DELAY BIOS API, but couldn't=20
> find it right now.
INT 15 - BIOS - WAIT (AT,PS)
AH = 86h
CX:DX = interval in microseconds
Return: CF clear if successful (wait interval elapsed)
CF set on error or AH=83h wait already in progress
AH = status (see #00496)
Note: the resolution of the wait period is 977 microseconds on many systems
because many BIOSes use the 1/1024 second fast interrupt from the AT
real-time clock chip which is available on INT 70
Port 0x61, by the way:
Bitfields for KB controller port B (system control port) [output]:
Bit(s) Description (Table P0392)
7 pulse to 1 for IRQ1 reset (PC,XT)
6-4 reserved
3 I/O channel parity check disable
2 RAM parity check disable
1 speaker data enable
0 timer 2 gate to speaker enable
---on WRITE, and on READ:---
7 RAM parity error occurred
6 I/O channel parity error occurred
5 mirrors timer 2 output condition
4 toggles with each refresh request
3 NMI I/O channel check status
2 NMI parity check status
1 speaker data status
0 timer 2 clock gate to speaker status
So the bit is the refresh timer - usually one of the 8254 timers,
the other two are used for speaker and irq 0 (int 8 / int 1c / 40[6c]
signal generation. On newer systems, the refresh is not done by 8254
anymore at all, but probably the timer is just available for general
use there, and the signal is still routed to port 61 test 10 for
compatibility reasons.
Other precision timers are:
RTC interrupt (see above)
IRQ0 timer (DJGPP can read the "current countdown value" to get some
clock / timestamp with roughly microsecond precision
TSC - time stamp counter, counting CPU clock cycles on Pentium-class/newer CPU
VGA - an IRQ can be generated at each vertical refresh (usually 60-200 Hz,
often only 60-72 for VGA/VESA modes)
...
But again, 55msec resolution is more than enough for a simple beep.
Eric
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