I was incorrect. The Freescale reference actually lists both numbers in the instruction list (167/231 in A.1 and A.5, 334/462 in A.2). The values you listed are correct, and match what GCC generates as well.
- Justin On Jan 17, 2017 13:49, "Roman Divacky" <[email protected]> wrote: > Are you sure? My coy of PowerISA lists the numbers that I used? What makes > you > think it should be shifted by one bit? > > On Mon, Jan 16, 2017 at 08:45:58PM -0600, Justin Hibbits wrote: > > The patch is incorrect, the 'xo' values are off by one bit (inline > > change): > > > > > > On Dec 5, 2016, at 10:19 AM, Roman Divacky wrote: > > > > > Can you try this patch? > > > > > > Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td > > > =================================================================== > > > --- llvm/lib/Target/PowerPC/PPCInstrInfo.td (revision 288675) > > > +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td (working copy) > > > @@ -2373,6 +2373,12 @@ > > > def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), > > > "mftb $RT, $SPR", IIC_SprMFTB>; > > > > > > +def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$PMRN), > > > > 334 should be 167 > > > > > + "mfpmr $RT, $PMRN", IIC_IntGeneral>; > > > + > > > +def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$PMRN, gprc:$RS), > > > + "mtpmr $PMRN, $RS", IIC_IntGeneral>; > > > > 462 should be 231. > > > > > + > > > // A pseudo-instruction used to implement the read of the 64-bit > > > cycle counter > > > // on a 32-bit target. > > > let hasSideEffects = 1, usesCustomInserter = 1 in > > > > > > > I'll have a patch ready for LLVM review within a week or so, including > > some level of scheduling. > > > > - Justin > _______________________________________________ [email protected] mailing list https://lists.freebsd.org/mailman/listinfo/freebsd-toolchain To unsubscribe, send any mail to "[email protected]"
