> Date: Sun, 1 Jul 2001 16:07:38 +0200
> From: Bernd Walter <[EMAIL PROTECTED]>
> In -currents NOTEs I found this:
> # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
> # reorder). This option should not be used if you use memory mapped
> # I/O device(s).
>
> A good sign that it may be at least possible on some CPUs.
> OK that's not an MP capable CPU.
This is an encouraging starting point... at least the issue is similar.
It's also in 4.3-R, so I can grep kernel source.
> What you need is an x86 guru or asume worst which will be the best
> thing anyway - otherwise you can't use it on other machines and
> sometimes programms get very old.
I thought that one had to assert "lock" to guarantee cache coherency...
an ugly hack would be to
movl (%pagebase,%index,1),%eax
lock movl %eax,(%pagebase,%index,1)
for every cache line in a page. Ugly and slow... I'd much rather find out
if there's a way to tell the chipset "flush all pending writes in this
block, and ensure that both CPUs have the same view".
> I also don't know what the following is:
> # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
> # K5/K6/K6-2 cpus.
Hmmmm. Being concerned about x86 SMP, I've overlooked anything non-Intel.
Might be worth checking out what's there... I've oft learned what I wanted
via an indirect route.
> > Did you try to read MP chipsets white papers?
No. I guess that I can give that a shot.
> I can't say very much about coherency problems on x86 but I can
> say for shure that you have to worry about this on every other MP
> platform including IA64.
Even if it's a non-issue on x86, I'd rather use macros to insert proper
code on ia64, axp (if I ever port to that), and go to nothing on x86 (if
that is indeed the correct behavior).
Looks like I need to do some digging on bus snooping, cache coherency,
read/write reordering, MTRRs, and APICs. :-)
Eddy
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