This patch tweaks various thresholds in the DP8381[56] chip.
On my Soekris 4801, the goes from 5-6 Mbit/sec to 30-40 Mbit/sec
with this patch.
Also included is Sams patch for the "short cable" problem".
Tests, comments etc most welcome.
Poul-Henning
Index: if_sis.c
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_sis.c,v
retrieving revision 1.80
diff -u -r1.80 if_sis.c
--- if_sis.c 27 Jul 2003 14:36:02 -0000 1.80
+++ if_sis.c 17 Aug 2003 10:46:59 -0000
@@ -107,7 +107,7 @@
static struct sis_type sis_devs[] = {
{ SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
{ SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
- { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" },
+ { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815/6 10/100BaseTX" },
{ 0, 0, NULL }
};
@@ -2031,6 +2031,10 @@
*/
sis_stop(sc);
+ if (sc->sis_type == SIS_TYPE_83815) {
+ CSR_WRITE_4(sc, NS_IHR, 0x120);
+ }
+
mii = device_get_softc(sc->sis_miibus);
/* Set MAC address */
@@ -2121,7 +2125,7 @@
if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
} else {
- CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
+ CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG128);
}
@@ -2144,6 +2148,29 @@
SIS_CLRBIT(sc, SIS_TX_CFG,
(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
+ }
+
+ if (sc->sis_type == SIS_TYPE_83815 &&
+ IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
+ uint32_t reg;
+
+ /*
+ * Some DP83815s experience problems when used with short
+ * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This
+ * sequence adjusts the DSP's signal attenuation to fix the
+ * problem.
+ */
+ CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
+
+ reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
+ CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000);
+ DELAY(100);
+ reg = CSR_READ_4(sc, NS_PHY_TDATA);
+ if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) {
+ CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
+ SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
+ }
+ CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}
/*
Index: if_sisreg.h
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_sisreg.h,v
retrieving revision 1.22
diff -u -r1.22 if_sisreg.h
--- if_sisreg.h 22 Jul 2003 01:35:09 -0000 1.22
+++ if_sisreg.h 17 Aug 2003 10:50:12 -0000
@@ -75,6 +75,7 @@
#define SIS_GPIO 0xB8
/* NS DP83815 registers */
+#define NS_IHR 0x1C
#define NS_CLKRUN 0x3C
#define NS_BMCR 0x80
#define NS_BMSR 0x84
@@ -237,12 +238,12 @@
#define SIS_TXDMA_256BYTES 0x00700000
#define SIS_TXCFG_100 \
- (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
- SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
+ (SIS_TXDMA_128BYTES|SIS_TXCFG_AUTOPAD|\
+ SIS_TXCFG_FILL(1024)|SIS_TXCFG_DRAIN(128))
#define SIS_TXCFG_10 \
(SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
- SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
+ SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(128))
#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
#define SIS_RXCFG_DMABURST 0x00700000
@@ -262,8 +263,8 @@
#define SIS_RXDMA_128BYTES 0x00600000
#define SIS_RXDMA_256BYTES 0x00700000
-#define SIS_RXCFG256 \
- (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
+#define SIS_RXCFG128 \
+ (SIS_RXCFG_DRAIN(128)|SIS_RXDMA_128BYTES)
#define SIS_RXCFG64 \
(SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES)
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
[EMAIL PROTECTED] | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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