...
> >As far as I can tell the fxp driver doesn't even use the tx_fifo in the
> >825xxx chips :-)
>
> The 82557-9 have a 2KB internal buffer for transmits. They don't start
> transmitting until a programmed threshold is reached - this is to insure
> that PCI bus latency doesn't result in the transmitter getting stalled.
> The fxp driver starts out with this threshold set at 512 bytes, but will
> increase it (512 bytes at a time) when a DMA underrun occurs. Of course
> once the threshold reached 1536, then an entire 1500 byte packet is DMA'd
> into the buffer before the transmit begins.
Can you point me to the part of if_fxp.c that does this, as alls I can find
about any form of fifo in the code are these references:
Guardian# grep -i fifo *fxp*
if_fxp.c: cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
if_fxp.c: cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
if_fxpreg.h: volatile u_int rx_fifo_limit:4,
if_fxpreg.h: tx_fifo_limit:3,
No place do I find anything that does any adjustments to these values :-(.
--
Rod Grimes - KD7CAX @ CN85sl - (RWG25) [EMAIL PROTECTED]
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