Adrian Chadd wrote:
> .. erm, sys/mips/mips/machdep.c:
>
> /*
> * call platform specific code to halt (until next interrupt) for the idle
> loop
> */
> void
> cpu_idle(int busy)
> {
> KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
> ("interrupts disabled in idle process."));
> KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
> ("all interrupts masked in idle process."));
>
> if (!busy) {
> critical_enter();
> cpu_idleclock();
> }
> __asm __volatile ("wait");
> if (!busy) {
> cpu_activeclock();
> critical_exit();
> }
> }
>
> .. does that look right?
Yes it does. x86 does the same, but with more details. The general idea
of the critical section is to block context switch out of idle thread
until missed time events will be handled inside cpu_activeclock().
Yes, this increases interrupt latency after long idle period. That's why
I have made it disabling under the high interrupt rate (busy flag set)
and written specially optimized hardclock() handler to be called only
once. Possibly same should be done to statclock() also.
--
Alexander Motin
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