> I understand that you can purchase special motherboards (probably only from
> AMD) for SMP K6-2's (possibly they'll take -3's as well). I doubt (without
> trying) the freebsd code supports this style as it's not done in the normal
> fashion. They kind of cheated the chips into working together. Not a great
> system. Either get a twin PII, or wait for the K7's (but that won't be
> cheap).
It is my understanding that the K7's require "OpenAPIC". The SMP code
would need to be updated for the non-APIC based implementation for
the K7's.
It's also my understanding that the K6 SMP architectures use the "BeBox"
PPC 603 SMP hack (the PPC 604's used in the SMP Apple boxes have
"processor attention" pins, and so don't suffer this handicap).
The hack involves using an ASIC in place of the L2 cache controllers
that would normally be associated with the chip. The result is that the
combined system supports only MEI cache coherency, instead of MESI cache
coherency.
FreeBSD's SMP really, really depends on MESI. Really. This means that
it would be very hard to port a working SMP over to another architecture
(e.g. SPARC, like Linux has), without abstracting the cache coherency
code out as a seperate (NULL on Intel) layer. In many ways, it was bad
to do SMP on Intel MPSpec compatible hardware, instead of starting with
lesser hardware and porting, since the implementation is tied to the
spec (for now).
Terry Lambert
te...@lambert.org
---
Any opinions in this posting are my own and not those of my present
or previous employers.
To Unsubscribe: send mail to majord...@freebsd.org
with "unsubscribe freebsd-current" in the body of the message
