On Tue, Mar 20, 2018 at 12:22:02PM +0100, Björn Tantau wrote: > > > Am 19. März 2018 18:21:36 MEZ schrieb Luc Verhaegen <[email protected]>: > >On Mon, Mar 19, 2018 at 05:01:06PM +0100, Björn Tantau wrote: > >> Am 19.03.2018 um 00:08 schrieb Luc Verhaegen: > >> > > >> >My current hypothesis: smsc at 0x480 > >> > > >> >Action required: 0x48E |= 0x10. > > > >> Do you want to scan for Super I/O sensors? (YES/no): Probing for > >Super-I/O at 0x2e/0x2f > >> Trying family `VIA/Winbond/Nuvoton/Fintek'... Yes > >> Found `Winbond W83627DHG Super IO Sensors' Success! > >> (address 0x290, driver `w83627ehf') > > > >Hrm. Perpendicular to what the bios that i got from AOpen tells me. > > > >Please mail a copy of your existing rom to me personally (exclude the > >flashrom ml, binary blobs should not go there). > > Here you go. Thanks for your help!
Ok, this shows how rusty i am with respect to flashrom. Not recognizing the + 0x0C as the typical offset for intel gpio line toggle. What this board needs is a call to intel_ich_gpio20_raise(); Will provide a patch later today. I am a bit worried though that the lpc io BAR is empty in your lspci. I am not sure whether that is handled in any way, and i do not think the intel gpio code in flashrom will deal with an empty bar gracefully. Luc Verhaegen. _______________________________________________ flashrom mailing list [email protected] https://mail.coreboot.org/mailman/listinfo/flashrom
