Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: bec02ea9de6ae8aec4a645b56424d7be999fe23f
https://github.com/tianocore/edk2/commit/bec02ea9de6ae8aec4a645b56424d7be999fe23f
Author: Ard Biesheuvel <[email protected]>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M MdePkg/Include/Library/ArmLib.h
Log Message:
-----------
MdePkg/ArmLib: Drop routines that maintain the entire D-cache
Cache maintenance on the D-cache hierarchy as a whole is not supported
by the ARM architecture, so drop the routines from ArmLib that pretend
to implement it.
Signed-off-by: Ard Biesheuvel <[email protected]>
Commit: 6706fe6e239253e45b28147e06f71dd68a374007
https://github.com/tianocore/edk2/commit/6706fe6e239253e45b28147e06f71dd68a374007
Author: Ard Biesheuvel <[email protected]>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
M ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
M ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
M ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c
M ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
M ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
Log Message:
-----------
ArmPkg/ArmLib: Drop set/way Dcache operations
Cache maintenance operations by set/way are not broadcast, and operate
on individual architected caches, making them suitable only for
en/disabling cache levels, which is the job of secure firmware, to be
carried out while the CPU in question is not taking part in the
cache coherency protocol.
Managing the clean/dirty state of a memory range can only be done using
cache maintenance by virtual address.
So drop the set/way handling from ArmLib for ARM and AARCH64, as there
is no context where it can be used correctly from EDK2.
Signed-off-by: Ard Biesheuvel <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/bb403511d412...6706fe6e2392
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