Branch: refs/heads/angushe/riscv-codegen
Home: https://github.com/dyninst/dyninst
Commit: 59e1cfba7aef86dcd141b58ce9fd57fa8ee1675e
https://github.com/dyninst/dyninst/commit/59e1cfba7aef86dcd141b58ce9fd57fa8ee1675e
Author: wxrdnx <[email protected]>
Date: 2025-04-10 (Thu, 10 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add Marco's patch
Commit: 9b9b9baa396c04bf6688303f48d88b61aa745b64
https://github.com/dyninst/dyninst/commit/9b9b9baa396c04bf6688303f48d88b61aa745b64
Author: wxrdnx <[email protected]>
Date: 2025-04-11 (Fri, 11 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Compare: https://github.com/dyninst/dyninst/compare/9e8804187bb4...9b9b9baa396c
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