Branch: refs/heads/angushe/riscv
Home: https://github.com/dyninst/dyninst
Commit: 49ca9375ba8fe8a5945e7b72d64d0dc2b05aefd9
https://github.com/dyninst/dyninst/commit/49ca9375ba8fe8a5945e7b72d64d0dc2b05aefd9
Author: wxrdnx <[email protected]>
Date: 2025-02-02 (Sun, 02 Feb 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: dba9ebb40419bd4711066675d4f444333c9373a8
https://github.com/dyninst/dyninst/commit/dba9ebb40419bd4711066675d4f444333c9373a8
Author: wxrdnx <[email protected]>
Date: 2025-02-02 (Sun, 02 Feb 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Compare: https://github.com/dyninst/dyninst/compare/1cbe905f4b96...dba9ebb40419
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