Branch: refs/heads/angushe/riscv
Home: https://github.com/dyninst/dyninst
Commit: 1c17f9d9f390755b6967779212d58d893f9f4ea0
https://github.com/dyninst/dyninst/commit/1c17f9d9f390755b6967779212d58d893f9f4ea0
Author: wxrdnx <[email protected]>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
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