Branch: refs/heads/master
Home: https://github.com/dyninst/dyninst
Commit: 254490e708d122f2824cafb5b95051127644ef5c
https://github.com/dyninst/dyninst/commit/254490e708d122f2824cafb5b95051127644ef5c
Author: Tim Haines <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
Fix aarch64 MachRegister -> ROSE register conversion (#1843)
* Fix PC conversion
This handles both the 32-bit and 64-bit SP representations.
* Update conversion of zero register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
* Update conversion of stack pointer
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
* Update conversion of pstate register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
* Update conversion of GPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
* Update conversion of FPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
* Update conversion of pstate flags
This makes it uniform with the other conversions. Note: the complete
pstate register is treated separately from its individual fields in
ROSE.
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