On Sun, Nov 04 2018, Sergio Paracuellos wrote: > Add missing system control registers address in pcie node of > the device tree. > > Signed-off-by: Sergio Paracuellos <[email protected]> > --- > drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi > b/drivers/staging/mt7621-dts/mt7621.dtsi > index 2e837e6..6b4bc43 100644 > --- a/drivers/staging/mt7621-dts/mt7621.dtsi > +++ b/drivers/staging/mt7621-dts/mt7621.dtsi > @@ -397,8 +397,8 @@ > reg = <0x1e140000 0x100 /* host-pci bridge registers */ > 0x1e142000 0x100 /* pcie port 0 RC control registers > */ > 0x1e143000 0x100 /* pcie port 1 RC control registers > */ > - 0x1e144000 0x100>; /* pcie port 2 RC control registers > */ > - > + 0x1e144000 0x100 /* pcie port 2 RC control registers > */ > + 0x1e000000 0x100>; /* sysctl */
This is no good. The sysctl register are already claimed by palmbus, so
pci fails to claim it.
The best way to access the sysc registers is to use
rt_sysc_[rwm]32().
Below is my current fix-up patch to deal with this.
Thanks,
NeilBrown
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 6b4bc43d8eb6..e1000690bef2 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -398,7 +398,7 @@
0x1e142000 0x100 /* pcie port 0 RC control registers
*/
0x1e143000 0x100 /* pcie port 1 RC control registers
*/
0x1e144000 0x100 /* pcie port 2 RC control registers
*/
- 0x1e000000 0x100>; /* sysctl */
+ >;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index aa9baa776923..be4680f9b43a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -172,7 +172,6 @@ struct mt7621_pcie_port {
/**
* struct mt7621_pcie - PCIe host information
* @base: IO Mapped Register Base
- * @sysctl: system control mapped register base
* @io: IO resource
* @mem: non-prefetchable memory resource
* @busn: bus range
@@ -182,7 +181,6 @@ struct mt7621_pcie_port {
*/
struct mt7621_pcie {
void __iomem *base;
- void __iomem *sysctl;
struct device *dev;
struct resource io;
struct resource mem;
@@ -397,8 +395,7 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
static void mt7621_enable_phy(struct mt7621_pcie_port *port)
{
- struct mt7621_pcie *pcie = port->pcie;
- u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+ u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
bypass_pipe_rst(port);
@@ -534,16 +531,6 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
- err = of_address_to_resource(node, 4, ®s);
- if (err) {
- dev_err(dev, "missing \"reg\" property\n");
- return err;
- }
-
- pcie->sysctl = devm_ioremap_resource(dev, ®s);
- if (IS_ERR(pcie->sysctl))
- return PTR_ERR(pcie->sysctl);
-
for_each_available_child_of_node(node, child) {
int slot;
@@ -637,11 +624,9 @@ static int mt7621_pcie_register_host(struct
pci_host_bridge *host,
static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
{
- u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
-
- reg &= ~(0x3 << 10 | 0x3 << 3);
- reg |= (BIT(10) | BIT(3));
- iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
+ rt_sysc_m32(0x3 << 10 | 0x3 << 3,
+ BIT(10) | BIT(3),
+ MT7621_GPIO_MODE);
mdelay(100);
}
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