This patch series include an attempt to avoid the use of custom
read and writes in driver code and use PCI subsystem common ones.
In order to do this 'map_bus' callback is implemented and also
data structures for driver are included. The regs base address
ranges and data is being readed from device tree and the driver
gets clean a lot of code.
This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
kernel api.
Changes in v10:
- PATCH 1: Do 'ioremap' directly using 'ranges.cpu_addr' from the
io resource and add it directly as a resource to the resources list
like mips pci-legacy code do for this. We cannot do anything else since
using new kernel pci generic apis (call to
'devm_of_pci_get_host_bridge_resources')
we get bad io resource getting 'OF_BAD_ADDR' because of the fact that the
io resource for this platform starts in 0x1e160000 which is higher than
IO_SPACE_LIMIT (0xFFFF). Because of this io resource is not added to the
resources
list and system gets into a not working state.
- Other patches rebased and adapted to this changes.
Changes in v9:
- PATCH 1: Use 'res' as resources list and void store resources in
the pcie data struct.
- PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use
'devm_of_pci_get_host_bridge_resources' and use 'remap' directly
with the returned 'iobase' address instead of 'devm_pci_remap_iospace'
which get into a WARN_ONCE statement because 'PCI_IOBASE' is not
defined for mips.
- Other patches rebased and adapted to this changes.
Changes in v8:
- PATCH 1: don't check 'of_pci_range_to_resource' return value which is not
being checked for the legacy code.
- PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and
setup_cm_memory_region'
after the port initialization code.
- PATCH 1: make use of 'pci_host_probe' to avoid code duplication in
function
'mt7621_pcie_register_host'.
- PATCH 1: set resource limits with no limit for the end in
'ioport_resource' and
'iomem_resource'. It seems mips needs this to work properly.
- Other patches rebased and adapted to this changes.
Changes in v7:
- PATCH 1: Store resources in mt7621_pci data structure.
- PATCH 1: Change completely function mt7621_pci_parse_request_of_pci_ranges
to parse resources from ranges manually instead of use the function
devm_of_pci_get_host_bridge_resources. This is closer to the mips pci
legacy
code.
- PATCH 1: Create 'mt7621_pcie_request_resources' function to request
resources
parsed from ranges property in the DT. Use pci_add_resource_offset and
set them
manually like the mips pci-legacy code do.
- PATCH 1: don't delete function setup_cm_memory_region and call it with
memory
resource.
- Other patches rebased and adapted to this changes.
Changes in v6:
- Reorder patches to be each patch correct in itself.
- PATCH 1 adds also Kconfig to do the step from legacy to generic code
- PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in
a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
- Other patches rebased and adapted with this changes.
Changes in v5:
- Include driver Kconfig file to add compilation depends of
PCI_DRIVERS_GENERIC.
The new added configuration option is CONFIG_PCI_MT7621.
- Add list_splice_init(&res, &bridge->windows); in PATCH 1 to set windows
from resources obtanined from devm_request_pci_bus_resources.
- Move devm_of_pci_get_host_bridge_resources and
devm_request_pci_bus_resources
after the ports initialization legacy code.
- Add pcie ports 1 and 2 RC registers to device tree. There was only being
included
port RC register for port 0.
- Review includes and order them alphabetically.
Changes in v4:
- Rebased onto staging-next.
Changes in v3:
- Include new patches to delete all RALINK_BASE definition
dependant code and be able to avoid use of pci_legacy code.
- use devm_of_pci_get_host_bridge_resources,
devm_request_pci_bus_resources and pci_scan_root_bus_bridge
and pci_bus_add_devices
Changes in v2:
- squash PATCH 1 and PATCH 2 of previous series in only PATCH 1
- Change name for host structure.
- Create a new port structure (platform has 3 pcie controllers)
- Replace the use of pci_generic_config_[read|write]32 in favour
of pci_generic_config_[read|write] and change map_bus implemen-
tation for hopefully the right one.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (15):
staging: mt7621-pci: use generic kernel pci subsystem read and write
staging: mt7621-pci: remove dead code derived to not use custom reads
and writes
staging: mt7621-pci: add pcie_write and pcie_read helpers
staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
staging: mt7621-pci: simplify read_config function
staging: mt7621-pci: simplify write_config function
staging: mt7621-pci: remove unused macros
staging: mt7621-pci: avoid register duplication per controller using
pcie_[read|write]
staging: mt7621-pci: review includes putting them in alphabethic order
staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR
and RALINK_PCI_PCIMSK_ADDR
staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
staging: mt7621-pci: use BIT macro in preprocessor definitions
staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
definition
staging: mt7621-pci: remove remaining pci_legacy dependant code
staging: mt7621-dts: add pcie controller port registers
drivers/staging/Kconfig | 2 +
drivers/staging/mt7621-dts/mt7621.dtsi | 6 +-
drivers/staging/mt7621-pci/Kconfig | 7 +
drivers/staging/mt7621-pci/pci-mt7621.c | 757 ++++++++++++++++----------------
4 files changed, 403 insertions(+), 369 deletions(-)
create mode 100644 drivers/staging/mt7621-pci/Kconfig
--
2.7.4
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