> -----Original Message-----
> From: Jiang Liu [mailto:[email protected]]
> Sent: Wednesday, December 2, 2015 10:53 PM
> To: Jake Oshins <[email protected]>; [email protected]; KY
> Srinivasan <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Haiyang Zhang
> <[email protected]>; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH v6 4/7] PCI: Add fwnode_handle to pci_sysdata
>
> On 2015/11/3 5:33, [email protected] wrote:
> > From: Jake Oshins <[email protected]>
> >
> > +#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
> > +static inline void *_pci_root_bus_fwnode(struct pci_bus *bus)
> > +{
> > + struct pci_sysdata *sd = bus->sysdata;
> > + return sd->fwnode;
> > +}
> > +
> > +#define pci_root_bus_fwnode _pci_root_bus_fwnode
> > +#endif
> > +
> > /* Can be used to override the logic in pci_scan_bus for skipping
> > already-configured bus numbers - to be used for buggy BIOSes
> > or architectures with incomplete PCI setup by the loader */
> > diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
> > index f24bc51..3fde985 100644
> > --- a/include/asm-generic/pci.h
> > +++ b/include/asm-generic/pci.h
> > @@ -21,4 +21,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev
> *dev, int channel)
> > #define PCI_DMA_BUS_IS_PHYS (1)
> > #endif
> >
> > +#ifndef pci_root_bus_fwnode
> > +#define pci_root_bus_fwnode(bus) ((void)(bus),NULL)
> > +#endif
> Hi Jakeo,
> For x86, all PCI devices share the same MSI controller. But I'm
> not sure whether it may have per-bus/per-device MSI controllers on other
> archs. If there may be multiple MSI controllers serving PCI devices
> under the same PCI root, it would be better to use some thing like
> pci_get_msi_fwnode(bus) or similar.
> Thanks,
> Gerry
>
Certainly other architectures have per-bus MSI controllers, though usually it's
per root complex. In case you're not familiar with PCI Express terms (and I
apologize for this if you are) a root complex is one instance of PCI Express,
where traffic is defined between every part of it. If your traffic leaves PCI
Express and goes onto some processor-specific bus, it has left the root
complex. The root complex is usually modeled as a root PCI bus, a set of root
port, and a set of legacy and/or embedded endpoints, which amounts to saying
that some PCI/E devices are built into the root complex and not connected with
links.
I don't have a use case at the moment for anything other than an MSI controller
for a root complex. If you'd like me to change this so that it more naturally
extends to a situation where you'd want to use it for a specific bus, I can do
that. Please let me know.
And thanks again for your review.
-- Jake Oshins
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