From 177c0de810f39fe1567eb05ee02bfd6492397b9c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Feb 2010 13:27:11 -0500 Subject: [PATCH] drm/radeon/kms/r7xx: fix spelling in struct - fize -> size - also move a bit field define next to the relevant register Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 2 +- drivers/gpu/drm/radeon/rv770.c | 10 +++++----- drivers/gpu/drm/radeon/rv770d.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9f35bee..814c332 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -831,7 +831,7 @@ struct rv770_asic { unsigned sx_num_of_sets; unsigned sc_prim_fifo_size; unsigned sc_hiz_tile_fifo_size; - unsigned sc_earlyz_tile_fifo_fize; + unsigned sc_earlyz_tile_fifo_size; unsigned tiling_nbanks; unsigned tiling_npipes; unsigned tiling_group_size; diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 2c10fae..3fce1e7 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -490,7 +490,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) rdev->config.rv770.sx_num_of_sets = 7; rdev->config.rv770.sc_prim_fifo_size = 0xF9; rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; - rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + rdev->config.rv770.sc_earlyz_tile_fifo_size = 0x130; break; case CHIP_RV730: rdev->config.rv770.max_pipes = 2; @@ -510,7 +510,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) rdev->config.rv770.sx_num_of_sets = 7; rdev->config.rv770.sc_prim_fifo_size = 0xf9; rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; - rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + rdev->config.rv770.sc_earlyz_tile_fifo_size = 0x130; if (rdev->config.rv770.sx_max_export_pos_size > 16) { rdev->config.rv770.sx_max_export_pos_size -= 16; rdev->config.rv770.sx_max_export_smx_size += 16; @@ -534,7 +534,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) rdev->config.rv770.sx_num_of_sets = 7; rdev->config.rv770.sc_prim_fifo_size = 0x40; rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; - rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + rdev->config.rv770.sc_earlyz_tile_fifo_size = 0x130; break; case CHIP_RV740: rdev->config.rv770.max_pipes = 4; @@ -554,7 +554,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) rdev->config.rv770.sx_num_of_sets = 7; rdev->config.rv770.sc_prim_fifo_size = 0x100; rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; - rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + rdev->config.rv770.sc_earlyz_tile_fifo_size = 0x130; if (rdev->config.rv770.sx_max_export_pos_size > 16) { rdev->config.rv770.sx_max_export_pos_size -= 16; @@ -712,7 +712,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | - SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); + SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_size))); WREG32(PA_SC_MULTI_CHIP_CNTL, 0); diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 9506f8c..2920887 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -180,6 +180,7 @@ #define PA_SC_FIFO_SIZE 0x8BCC #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) +#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) @@ -187,7 +188,6 @@ #define PA_SC_LINE_STIPPLE_STATE 0x8B10 #define PA_SC_MODE_CNTL 0x28A4C #define PA_SC_MULTI_CHIP_CNTL 0x8B20 -#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) #define SCRATCH_REG0 0x8500 #define SCRATCH_REG1 0x8504 -- 1.5.6.3