2010/2/7 Émeric Maschino <[email protected]>:
> I've no idea about sideband addressing. Is there a way to check
> whether it's enabled or not? And is there a way to disable it?
lspci -vv gives:
80:00.0 VGA compatible controller: ATI Technologies Inc Radeon R300 NG
[FireGL X1] (rev 80) (prog-if 00 [VGA controller])
Subsystem: ATI Technologies Inc Device 0152
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping+ SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 192 (2000ns min), Cache Line Size: 128 bytes
Interrupt: pin A routed to IRQ 61
Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M]
Region 1: I/O ports at 8000 [size=256]
Region 2: Memory at d8030000 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at d8000000 [disabled] [size=128K]
Capabilities: [58] AGP version 2.0
Status: RQ=80 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans-
64bit-
FW+ AGP3- Rate=x1,x2,x4
Command: RQ=16 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW-
Rate=x4
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
80:00.1 Display controller: ATI Technologies Inc Radeon R300 [FireGL
X1] (Secondary) (rev 80)
Subsystem: ATI Technologies Inc Device 0153
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping+ SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 192 (2000ns min), Cache Line Size: 128 bytes
Region 0: Memory at c8000000 (32-bit, prefetchable) [size=128M]
Region 1: Memory at d8020000 (32-bit, non-prefetchable) [size=64K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
I imagine that SBA+ stands for SideBand Addressing enabled, right? I
still don't know how to disable it.
Émeric
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