Luca Barbieri wrote: > When designing this, we should also keep in mind that some drivers > (e.g. nouveau) have multiple FIFO channels, and thus we would like a > buffer to be referenced for reading by multiple channels at once (and > be destroyed only when all fences are expired, obviously). > Also, hardware may support on-GPU inter-channel synchronization, and > then multiple references may be for writing too. >
In the context of the current code, I've been thinking of having a list of fences on each bo to support multiple readers, and also to try to deal with the problem of simultaneous GPU- and CPU readers. But if the hardware supports on-GPU inter-channel synchronization, I figure the code should be smart enough to only wait on the "last" write fence? /Thomas ------------------------------------------------------------------------------ Throughout its 18-year history, RSA Conference consistently attracts the world's best and brightest in the field, creating opportunities for Conference attendees to learn about information security's most important issues through interactions with peers, luminaries and emerging and established companies. http://p.sf.net/sfu/rsaconf-dev2dev -- _______________________________________________ Dri-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-devel
