For those of you having issues with the spread spectrum patch, this
patch should fix it up. If not, we should probably get rid the ss
patch until it's gotten some more testing.
Alex
From 4a5d68c399f950bd603e7af752ac7eb430ee1d19 Mon Sep 17 00:00:00 2001
From: Alex Deucher <[email protected]>
Date: Tue, 27 Oct 2009 16:31:26 -0400
Subject: [PATCH] drm/radeon/kms/atom: force disable spread spectrum
Only attempt to enable it if LVDS.
Signed-off-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/radeon/atombios_crtc.c | 34 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/radeon/radeon_reg.h | 5 ++++
2 files changed, 38 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 8516e1b..cbf45cf 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -351,6 +351,35 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}
+static void radeon_disable_ss(struct drm_crtc *crtc)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t tmp;
+
+ if (ASIC_IS_AVIVO(rdev)) {
+ if (radeon_crtc->crtc_id == 0) {
+ tmp = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
+ WREG32(AVIVO_P1PLL_INT_SS_CNTL, tmp & ~1);
+ } else {
+ tmp = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
+ WREG32(AVIVO_P2PLL_INT_SS_CNTL, tmp & ~1);
+ }
+ } else {
+ tmp = RREG32(RADEON_LVDS_SS_GEN_CNTL);
+ if (((tmp & RADEON_SS_EXT_SEL) && (radeon_crtc->crtc_id == 1)) ||
+ ((!(tmp & RADEON_SS_EXT_SEL)) && (radeon_crtc->crtc_id == 0)))
+ WREG32(RADEON_LVDS_SS_GEN_CNTL, tmp & ~RADEON_SS_EXT_EN);
+ if (rdev->family >= CHIP_R200) {
+ tmp = RREG32_PLL(R200_SS_INT_CONTROL);
+ if (((tmp & R200_SS_INT_SEL) && (radeon_crtc->crtc_id == 1)) ||
+ ((!(tmp & R200_SS_INT_SEL)) && (radeon_crtc->crtc_id == 0)))
+ WREG32_PLL(R200_SS_INT_CONTROL, tmp & ~R200_SS_INT_EN);
+ }
+ }
+}
+
static void atombios_set_ss(struct drm_crtc *crtc, int enable)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -376,7 +405,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
step = dig->ss->step;
delay = dig->ss->delay;
range = dig->ss->range;
- } else if (enable)
+ } else
return;
break;
}
@@ -691,8 +720,11 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
/* TODO color tiling */
+ /* disable ss */
+ radeon_disable_ss(crtc);
atombios_set_ss(crtc, 0);
atombios_crtc_set_pll(crtc, adjusted_mode);
+ /* possibly enable it if lvds */
atombios_set_ss(crtc, 1);
atombios_crtc_set_timing(crtc, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 29ab759..599c219 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1115,8 +1115,13 @@
# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
# define R300_LVDS_SRC_SEL_RMX (2 << 18)
#define RADEON_LVDS_SS_GEN_CNTL 0x02ec
+# define RADEON_SS_EXT_EN (1 << 1)
+# define RADEON_SS_EXT_SEL (1 << 2)
# define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16
# define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20
+#define R200_SS_INT_CONTROL 0x0033 /* PLL */
+# define R200_SS_INT_EN (1 << 0)
+# define R200_SS_INT_SEL (1 << 1)
#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
#define RADEON_DISPLAY_BASE_ADDR 0x23c
--
1.5.6.3
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