http://bugs.freedesktop.org/show_bug.cgi?id=15472





--- Comment #3 from Jie Luo <[EMAIL PROTECTED]>  2008-04-20 22:01:18 PST ---
(In reply to comment #2)
> After reading the graphic core document from intel video driver site. I did
> some debug. Here is the result of dump debug register.
> 
> This is the regdump of normal state.
> IPEIR: 0 IPEHR: 0
> EIR: 0 ESR: 0 EMR: 0xffff
> INSTDONE: 0xffc0 INSTPM: 0
> MEMMODE: 0x306  INSTPS: 0xf0000 
> HWSTAM: 0xfffe IER: 0x2 IMR: 0 IIR: 0x20
> 
> This is the regdump of the state ESR being set to 0x00000001.
> IPEIR: 0 IPEHR: 0
> EIR: 0 ESR: 0x1 EMR: 0xffff
> INSTDONE: 0xffc0 INSTPM: 0
> MEMMODE: 0x306  INSTPS: 0xf0000 
> HWSTAM: 0xfffe IER: 0xa2 IMR: 0 IIR: 0x50
> 
> According to the document, ESR being set to 0x1 indicate Instruction Error. 
> The
> document said that IPEHR register contains the header (DWord 0) of the 
> faulting
> instruction. So the faulting instruction is a MI instruction. IER being set to
> be 0xa2 means 'Display Plane C Flip Pending' and 'Display Pipe B VBLANK' is
> enabled. But because I don't have a PIPE C, this means the Instruction Error 
> is
> caused by a MI_DISPLAY_BUFFER_INFO instruction with a defeatured opcode (PIPE
> C). Any comments?
> 

It seams that my thought above is not correct. The only thing I'm sure is that
glXSwapBuffers() may cause this instruction error. My test is done with glxdemo
program. With LIBGL_ALWAYS_INDIRECT=1, glxdemo doesn't cause instruction error
without call glXSwapBuffers(), but will cause this error with glXSwapBuffers()
after some resizing and moving. I give up to track down this problem, it too
complicated for me to do this.


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