http://bugs.freedesktop.org/show_bug.cgi?id=13080
------- Comment #17 from [EMAIL PROTECTED] 2007-11-12 10:35 PST ------- (In reply to comment #16) > Yeah, the depth buffer on rv100 is not tiled until you enable hyperz. This is > something that was never fixed in mesa's pixel span routines, these assume > that > the depth buffer is always tiled. Oops. I thought that was fixed ages ago. But looks like it's not... In fact this looks pretty strange, in the dri driver depthHasSurface is set according to ddx version (which is ok) and according to RADEON_CHIPSET_TCL - this isn't the same for all radeon families (at least ddx doesn't set it up like that, maybe fallout from merging r100/r200/r300 radeon_screen.c), so would break r200/r300 igps. But even for r100, this sounds wrong as it only decides if we're using software z-buffer de-tiling or not - for chips which really don't use z tiling we should just pretend we have a surface set up for tiling anyway since we can just read it directly without address translation... Chris, does it work correctly if you remove the additional test for RADEON_CHIPSET_TCL in that screen->depthHasSurface assignment in radeon_screen.c? -- Configure bugmail: http://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug, or are watching the assignee. ------------------------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now >> http://get.splunk.com/ -- _______________________________________________ Dri-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-devel
