On 6/21/05, Aapo Tahkola <[EMAIL PROTECTED]> wrote:
> On Thu, 16 Jun 2005 14:22:36 +0200
> Nicolai Haehnle <[EMAIL PROTECTED]> wrote:
>
> > On Thursday 16 June 2005 13:41, Aapo Tahkola wrote:
> > > Update of /cvsroot/r300/r300_driver/r300
> > > In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6333
> > >
> > > Modified Files:
> > > r300_reg.h r300_state.c
> > > Log Message:
> > > Use depth tiling.
> >
> > Will this work with software fallbacks?
>
> Im not quite sure but more recent r200_span.c has few words about it.
> Attached patch enables color tiling in case someone wants to play with it.
>
> --
> Aapo Tahkola
>
>
>
I've done some looking into tiling on r3/4xx hardware, and this patch
isn't quite right. this works as long as the offset is 0, however, if
you adjust the frame certain offsets don't work. they actually made
tiling work much easier on r3/4xx hardware. when tiling is enabled,
crtc_offset is used to hold the address of the surface and a new
x_y_tile reg is used for the actual offset. all you need to do is
plug in the x and y values and the hardware takes care of the rest, no
moer complicated tile address calculations.
Here's the working version of doadjustframe() (to be used in
conjunction with your patch:
void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, int clone)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int reg, Base, regcntl, crtcoffsetcntl, xytilereg, crtcxytile;
#ifdef XF86DRI
RADEONSAREAPrivPtr pSAREAPriv;
XF86DRISAREAPtr pSAREA;
#endif
Base = pScrn->fbOffset;
/* note we cannot really simply use the
info->ModeReg.crtc_offset_cntl value, since the
drm might have set FLIP_CNTL since we wrote that. Unfortunately
FLIP_CNTL causes
flickering when scrolling vertically in a virtual screen,
possibly because crtc will
pick up the new offset value at the end of each scanline, but the
new offset_cntl value
only after a vsync. We'd probably need to wait (in drm) for vsync
and only then update
OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
if (clone || info->IsSecondary) {
reg = RADEON_CRTC2_OFFSET;
regcntl = RADEON_CRTC2_OFFSET_CNTL;
xytilereg = R300_CRTC2_TILE_X0_Y0;
} else {
reg = RADEON_CRTC_OFFSET;
regcntl = RADEON_CRTC_OFFSET_CNTL;
xytilereg = R300_CRTC_TILE_X0_Y0;
}
crtcoffsetcntl = INREG(regcntl) & ~0xf;
/* try to get rid of flickering when scrolling at least for 2d */
#ifdef XF86DRI
if (!info->have3DWindows)
#endif
crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
if (info->tilingEnabled) {
if (IS_R300_VARIANT) {
/* On r300/r400 when tiling is enabled crtc_offset is set to the
address of
* the surface. the x/y offsets are handled by the X_Y tile reg for
each crtc
* Makes tiling MUCH easier.
*/
crtcxytile = x | (y << 16);
Base &= ~0x7ff;
} else {
int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
/* crtc uses 256(bytes)x8 "half-tile" start addresses? */
int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth +
x) >> (8 - byteshift)) << 11;
Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
crtcoffsetcntl = crtcoffsetcntl | (y % 16);
}
}
else {
Base += y * info->CurrentLayout.displayWidth + x;
switch (info->CurrentLayout.pixel_code) {
case 15:
case 16: Base *= 2; break;
case 24: Base *= 3; break;
case 32: Base *= 4; break;
}
}
Base &= ~7; /* 3 lower bits are always 0 */
#ifdef XF86DRI
if (info->directRenderingEnabled) {
/* note cannot use pScrn->pScreen since this is unitialized when called
from
RADEONScreenInit, and we need to call from there to get mergedfb +
pageflip working */
pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
/* can't get at sarea in a semi-sane way? */
pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
if (clone || info->IsSecondary) {
pSAREAPriv->crtc2_base = Base;
}
else {
pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes)
% info->CurrentLayout.displayWidth;
pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
/ info->CurrentLayout.displayWidth;
pSAREA->frame.width = pScrn->frameX1 - x + 1;
pSAREA->frame.height = pScrn->frameY1 - y + 1;
}
if (pSAREAPriv->pfCurrentPage == 1) {
Base += info->backOffset;
}
}
#endif
OUTREG(reg, Base);
if (IS_R300_VARIANT) {
OUTREG(xytilereg, crtcxytile);
} else {
OUTREG(regcntl, crtcoffsetcntl);
}
}
And here are the relevant new bitfields:
#define RADEON_CRTC_OFFSET_CNTL 0x0228
# define RADEON_CRTC_TILE_LINE_SHIFT 0
# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
# define R300_CRTC_X_Y_MODE_EN (1 << 9)
# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
# define R300_CRTC_MICRO_TILE_EN (1 << 13)
# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
# define R300_CRTC_MACRO_TILE_EN (1 << 15)
# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
# define RADEON_CRTC_TILE_EN (1 << 15)
# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
#define R300_CRTC_TILE_X0_Y0 0x0350
#define R300_CRTC2_TILE_X0_Y0 0x0358
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