Hi,
I tested latest CVS of r300 driver. Card is Rageon 9700Pro (NE).
I tested immediate and VB mode, both of them work ok - no locks (tested in glxgearx, tuxracer, nehe lesson06) . Even with x11perf -shmput 500 I can not lock machne.
Some screenshots from enemy territory (VB mode): http://www.gaya.sk/~pzubaj/scr/et1.jpg http://www.gaya.sk/~pzubaj/scr/et2.jpg http://www.gaya.sk/~pzubaj/scr/et3.jpg http://www.gaya.sk/~pzubaj/scr/et4.jpg http://www.gaya.sk/~pzubaj/scr/et5.jpg http://www.gaya.sk/~pzubaj/scr/et6.jpg
I trayed attached patch. With this patch still everything works ok - no lock.
Then I removed all occurrence of (from r300 driver):
reg_start(0x4f18,0); e32(0x00000003);
Still everything works ok - no lock.
Then I removed every
reg_start(R300_RB3D_DSTCACHE_CTLSTAT,0); e32(0x0000000a);
computer immediately lock.
For me looks like (my opinions): R300_RB3D_DSTCACHE_CTLSTAT is needs to be regural inserted to stream.
Register 0x4f18 is only need at begin and end of 3d drawing.
Peter Zubaj
diff -u o/radeon_cp.c n/radeon_cp.c
--- o/radeon_cp.c 2005-01-02 07:18:39.000000000 +0100
+++ n/radeon_cp.c 2005-02-18 21:36:51.000000000 +0100
@@ -984,32 +984,14 @@
RING_LOCALS;
DRM_DEBUG("\n");
- if (IS_FAMILY_R300(dev_priv)) {
- BEGIN_RING( 10 );
-
- OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0x00000002);
- OUT_RING_REG(0x4F18, 0x00000001); /* Z cache? */
-
- /* It seems a delay is needed */
- OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) );
- OUT_RING( 0x0 );
-
- RADEON_PURGE_CACHE();
-
- RADEON_WAIT_UNTIL_IDLE();
-
- ADVANCE_RING();
- } else {
+ BEGIN_RING(6);
- BEGIN_RING(6);
+ RADEON_PURGE_CACHE();
+ RADEON_PURGE_ZCACHE();
+ RADEON_WAIT_UNTIL_IDLE();
- RADEON_PURGE_CACHE();
- RADEON_PURGE_ZCACHE();
- RADEON_WAIT_UNTIL_IDLE();
+ ADVANCE_RING();
- ADVANCE_RING();
- }
-
COMMIT_RING();
return radeon_do_wait_for_idle(dev_priv);
diff -u o/radeon_state.c n/radeon_state.c
--- o/radeon_state.c 2005-02-13 11:35:54.000000000 +0100
+++ n/radeon_state.c 2005-02-18 21:38:41.000000000 +0100
@@ -1021,16 +1021,11 @@
/* Wait for the 3D stream to idle before dispatching the bitblt.
* This will prevent data corruption between the two streams.
*/
- if (IS_FAMILY_R300(dev_priv)) {
- /* Make sure the new caches are flushed */
- radeon_do_cp_idle(dev_priv);
- } else {
- BEGIN_RING(2);
+ BEGIN_RING(2);
- RADEON_WAIT_UNTIL_3D_IDLE();
+ RADEON_WAIT_UNTIL_3D_IDLE();
- ADVANCE_RING();
- }
+ ADVANCE_RING();
for (i = 0; i < nbox; i++) {
int x = pbox[i].x1;
@@ -1348,9 +1343,12 @@
*/
if (IS_FAMILY_R300(dev_priv)) {
- BEGIN_RING(10);
- OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0x00000002);
- OUT_RING_REG(0x4F18, 0x00000001); /* Z cache? */
+ /*BEGIN_RING(10);*/
+ BEGIN_RING(8);
+ /*OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0x00000002);
+ OUT_RING_REG(0x4F18, 0x00000001);*/ /* Z cache? */
+
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0x0000000A);
/* It seems a delay is needed */
OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) );
