On Sat, 2005-01-15 at 18:55 +0100, Jerome Glisse wrote:
> On Sat, 15 Jan 2005 12:22:24 -0500 (EST), Vladimir Dergachev
> <[EMAIL PROTECTED]> wrote:
> > >>
> > >> #define R300_SURFACE_CNTL       0xb00
> > >> #       define R300_SURFACE_TRANSLATION_DISABLE (1<<8)  /* this is 
> > >> default */
> > >>
> > >> #       define R300_SURFACE_AP0_LITTLE_ENDIAN   (0<<20)
> > >> #       define R300_SURFACE_AP0_16_BIG_ENDIAN   (1<<20)
> > >> #       define R300_SURFACE_AP0_32_BIG_ENDIAN   (2<<20)
> > >>
> > >> #       define R300_SURFACE_AP1_LITTLE_ENDIAN   (0<<22)
> > >> #       define R300_SURFACE_AP1_16_BIG_ENDIAN   (1<<22)
> > >> #       define R300_SURFACE_AP1_32_BIG_ENDIAN   (2<<22)
> > >
> > > Do not see sere to put this and when to use them.
> > > During engine setup or in r300 state ?
> 
> Do it before init3d and it changes nothings (at least visualy).

This register is set up by the DDX driver for the screen pixel format
and only applies to direct CPU framebuffer access.


> Anyway like i said the 0x2140 register have to be set to 2 on PPC.
> there is maybe somewhere else a similar register for host blt 

Sure, the HOST_DATA_SWAP bits... I've been meaning to play with
DP_SRC_ENDIAN instead.

> or they use another way like selecting appropriate texture format.
> For example if we are on ppc a texture that has argb8888 format
> on x86 is set to be bgra8888. See what i mean ? Thus we get the
> texture data swapping simply by changing texture format.

While this example might be possible, I don't think that's true for all
texture formats.


-- 
Earthling Michel DÃnzer      |     Debian (powerpc), X and DRI developer
Libre software enthusiast    |   http://svcs.affero.net/rm.php?r=daenzer


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