? Makefile ? agp.diff ? cobfixes.diff ? core-rework.diff ? savage.4.html ? savage._man ? streams_cleanup.diff ? streams_cleanup_big-v2.diff ? streams_cleanup_big-v3.diff ? streams_cleanup_big.diff ? twister.diff ? twister2.diff Index: savage_accel.c =================================================================== RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/savage/savage_accel.c,v retrieving revision 1.19 diff -u -r1.19 savage_accel.c --- savage_accel.c 26 Mar 2004 17:09:04 -0000 1.19 +++ savage_accel.c 30 Mar 2004 18:56:21 -0000 @@ -212,10 +212,13 @@ void writescan( unsigned long scan, unsigned long color ); static int GetTileAperturePitch(ulong dwWidth, ulong dwBpp); -void SavageSetGBD_M7(ScrnInfoPtr pScrn); +void SavageSetGBD_M7(ScrnInfoPtr pScrn); +void SavageSetGBD_3D(ScrnInfoPtr pScrn); void SavageSetGBD_Twister(ScrnInfoPtr pScrn); void SavageSetGBD_PM(ScrnInfoPtr pScrn); +#if 0 void SavageSetGBD_2000(ScrnInfoPtr pScrn); +#endif /* * This is used to cache the last known value for routines we want to @@ -450,6 +453,8 @@ */ switch (psav->Chipset) { case S3_SAVAGE3D: + SavageSetGBD_3D(pScrn); + break; case S3_SAVAGE_MX: SavageSetGBD_M7(pScrn); break; @@ -457,14 +462,12 @@ case S3_TWISTER: case S3_PROSAVAGE: case S3_PROSAVAGEDDR: + case S3_SAVAGE2000: SavageSetGBD_Twister(pScrn); break; case S3_SUPERSAVAGE: SavageSetGBD_PM(pScrn); break; - case S3_SAVAGE2000: - SavageSetGBD_2000(pScrn); - break; } } @@ -475,12 +478,13 @@ uchar byte; int bci_enable, tile16, tile32; - if (psav->Chipset == S3_SAVAGE4) { + if ((psav->Chipset == S3_SAVAGE4) + || (psav->Chipset == S3_TWISTER)) { bci_enable = BCI_ENABLE; - tile16 = TILE_FORMAT_DESTINATION16; - tile32 = TILE_FORMAT_DESTINATION32; + tile16 = TILE_FORMAT_16BPP; + tile32 = TILE_FORMAT_32BPP; } else { - bci_enable = BCI_ENABLE_TWISTER; + bci_enable = BCI_ENABLE_2000; tile16 = TILE_DESTINATION; tile32 = TILE_DESTINATION; } @@ -644,8 +648,8 @@ int bci_enable, tile16, tile32; bci_enable = BCI_ENABLE; - tile16 = TILE_FORMAT_DESTINATION16; - tile32 = TILE_FORMAT_DESTINATION32; + tile16 = TILE_FORMAT_16BPP; + tile32 = TILE_FORMAT_32BPP; /* following is the enable case */ @@ -837,6 +841,165 @@ byte = INREG8(SEQ_DATA_REG) & ~0X20; OUTREG8(SEQ_DATA_REG,byte); } + +void SavageSetGBD_3D(ScrnInfoPtr pScrn) +{ + SavagePtr psav = SAVPTR(pScrn); + ulong ulTmp; + uchar byte; + int bci_enable, tile16, tile32; + + /* same as M7, but different streams engine */ + + bci_enable = BCI_ENABLE; + tile16 = TILE_FORMAT_16BPP; + tile32 = TILE_FORMAT_32BPP; + + + /* following is the enable case */ + + /* SR01:turn off screen */ + OUTREG8 (SEQ_ADDRESS_REG,0x01); + byte = INREG8(SEQ_DATA_REG) | 0x20; + OUTREG8(SEQ_DATA_REG,byte); + + /* + * CR67_3: + * = 1 stream processor MMIO address and stride register + * are used to control the primary stream + * = 0 standard VGA address and stride registers + * are used to control the primary streams + */ + OUTREG8(CRT_ADDRESS_REG,0x67); + byte = INREG8(CRT_DATA_REG) | 0x08; + OUTREG8(CRT_DATA_REG,byte); + + + /* MM81C0 and 81C4 are used to control primary stream. */ + OUTREG32(PRI_STREAM_FBUF_ADDR0,0x00000000); + OUTREG32(PRI_STREAM_FBUF_ADDR1,0x00000000); + + /* + * Program Primary Stream Stride Register. + * + * Tell engine if tiling on or off, set primary stream stride, and + * if tiling, set tiling bits/pixel and primary stream tile offset. + * Note that tile offset (bits 16 - 29) must be scanline width in + * bytes/128bytespertile * 256 Qwords/tile. This is equivalent to + * lDelta * 2. Remember that if tiling, lDelta is screenwidth in + * bytes padded up to an even number of tilewidths. + */ + if (!psav->bTiled) { + OUTREG32(PRI_STREAM_STRIDE, + (((psav->lDelta * 2) << 16) & 0x3FFF0000) | + (psav->lDelta & 0x00003fff)); + } else if (pScrn->bitsPerPixel == 16) { + /* Scanline-length-in-bytes/128-bytes-per-tile * 256 Qwords/tile */ + OUTREG32(PRI_STREAM_STRIDE, + (((psav->lDelta * 2) << 16) & 0x3FFF0000) + | 0x80000000 | (psav->lDelta & 0x00003fff)); + } else if (pScrn->bitsPerPixel == 32) { + OUTREG32(PRI_STREAM_STRIDE, + (((psav->lDelta * 2) << 16) & 0x3FFF0000) + | 0xC0000000 | (psav->lDelta & 0x00003fff)); + } + + OUTREG32(0x8128, 0xFFFFFFFFL); + OUTREG32(0x812C, 0xFFFFFFFFL); + + OUTREG32(S3_BCI_GLB_BD_HIGH, bci_enable | S3_LITTLE_ENDIAN | S3_BD64); + + /* CR50, bit 7,6,0 = 111, Use GBD.*/ + OUTREG8(CRT_ADDRESS_REG,0x50); + byte = INREG8(CRT_DATA_REG) | 0xC1; + OUTREG8(CRT_DATA_REG, byte); + + /* + * CR78, bit 3 - Block write enabled(1)/disabled(0). + * bit 2 - Block write cycle time(0:2 cycles,1: 1 cycle) + * Note: Block write must be disabled when writing to tiled + * memory. Even when writing to non-tiled memory, block + * write should only be enabled for certain types of SGRAM. + */ + OUTREG8(CRT_ADDRESS_REG,0x78); + /*byte = INREG8(CRT_DATA_REG) & ~0x0C;*/ + byte = INREG8(CRT_DATA_REG) | 0xfb; + OUTREG8(CRT_DATA_REG,byte); + + /* + * Tiled Surface 0 Registers MM48C40: + * bit 0~23: tile surface 0 frame buffer offset + * bit 24~29:tile surface 0 width + * bit 30~31:tile surface 0 bits/pixel + * 00: reserved + * 01, 8 bits + * 10, 16 Bits. + * 11, 32 Bits. + */ + /* + * Global Bitmap Descriptor Register MM816C + * bit 24~25: tile format + * 00: linear + * 01: reserved + * 10: 16 bit + * 11: 32 bit + * bit 28: block write disble/enable + * 0: enable + * 1: disable + */ + if (!psav->bTiled) { + /* + * Do not enable block_write even for non-tiling modes, because + * the driver cannot determine if the memory type is the certain + * type of SGRAM for which block_write can be used. + */ + psav->GlobalBD.bd1.HighPart.ResBWTile = TILE_FORMAT_LINEAR;/* linear */ + + } + else if (pScrn->bitsPerPixel == 16) { + psav->GlobalBD.bd1.HighPart.ResBWTile = tile16;/* 16 bit */ + + ulTmp = ((psav->lDelta / 2) >> 6) << 24; + OUTREG32(TILED_SURFACE_REGISTER_0,ulTmp | TILED_SURF_BPP16); + } + else if (pScrn->bitsPerPixel == 32) { + psav->GlobalBD.bd1.HighPart.ResBWTile = tile32;/* 32 bit */ + + ulTmp = ((psav->lDelta / 4) >> 5) << 24; + OUTREG32(TILED_SURFACE_REGISTER_0,ulTmp | TILED_SURF_BPP32); + } + + psav->GlobalBD.bd1.HighPart.ResBWTile |= 0x10;/* disable block write */ + /* HW uses width */ + psav->GlobalBD.bd1.HighPart.Stride = (ushort)(psav->lDelta / (pScrn->bitsPerPixel >> 3)); + psav->GlobalBD.bd1.HighPart.Bpp = (uchar) (pScrn->bitsPerPixel); + psav->GlobalBD.bd1.Offset = 0; + + + /* + * CR31, bit 0 = 0, Disable address offset bits(CR6A_6-0). + * bit 0 = 1, Enable 8 Mbytes of display memory thru 64K window + * at A000:0. + */ + OUTREG8(CRT_ADDRESS_REG,MEMORY_CONFIG_REG); /* cr31 */ + byte = INREG8(CRT_DATA_REG) & (~(ENABLE_CPUA_BASE_A0000)); + OUTREG8(CRT_DATA_REG,byte); + + /* program the GBD and SBD's */ + OUTREG32(S3_GLB_BD_LOW,psav->GlobalBD.bd2.LoPart ); + /* 8: bci enable */ + OUTREG32(S3_GLB_BD_HIGH,(psav->GlobalBD.bd2.HiPart + | bci_enable | S3_LITTLE_ENDIAN | S3_BD64)); + OUTREG32(S3_PRI_BD_LOW,psav->GlobalBD.bd2.LoPart); + OUTREG32(S3_PRI_BD_HIGH,psav->GlobalBD.bd2.HiPart); + OUTREG32(S3_SEC_BD_LOW,psav->GlobalBD.bd2.LoPart); + OUTREG32(S3_SEC_BD_HIGH,psav->GlobalBD.bd2.HiPart); + + /* turn on screen */ + OUTREG8(SEQ_ADDRESS_REG,0x01); + byte = INREG8(SEQ_DATA_REG) & ~0X20; + OUTREG8(SEQ_DATA_REG,byte); +} void SavageSetGBD_PM(ScrnInfoPtr pScrn) { @@ -848,7 +1011,7 @@ /* Is supersavage like savage4 or twister? * change the bci_enable and tile bits here. */ - bci_enable = BCI_ENABLE_TWISTER; + bci_enable = BCI_ENABLE_2000; tile16 = TILE_DESTINATION; tile32 = TILE_DESTINATION; @@ -995,6 +1158,7 @@ OUTREG8(SEQ_DATA_REG,byte); } +#if 0 void SavageSetGBD_2000(ScrnInfoPtr pScrn) { vgaHWPtr hwp = VGAHWPTR(pScrn); @@ -1036,6 +1200,7 @@ OUTREG(PRI_STREAM_STRIDE, pScrn->displayWidth * pScrn->bitsPerPixel >> 3); OUTREG(SEC_STREAM_STRIDE, pScrn->displayWidth * pScrn->bitsPerPixel >> 3); } +#endif /* Acceleration init function, sets up pointers to our accelerated functions */ Index: savage_bci.h =================================================================== RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/savage/savage_bci.h,v retrieving revision 1.2 diff -u -r1.2 savage_bci.h --- savage_bci.h 22 Feb 2004 16:14:42 -0000 1.2 +++ savage_bci.h 30 Mar 2004 18:56:21 -0000 @@ -20,15 +20,14 @@ #define TILE_FORMAT_LINEAR 0 #define TILE_TEXTURE 2 #define TILE_DESTINATION 1 -#define TILE_FORMAT_DESTINATION16 2 -#define TILE_FORMAT_DESTINATION32 3 +#define TILE_FORMAT_16BPP 2 +#define TILE_FORMAT_32BPP 3 /* BD - BCI enable */ -/* savage4, MX, IX, 3D */ +/* savage4, twister?, MX, IX, 3D */ #define BCI_ENABLE 8 -/* twister, prosavage */ -/* not sure which one supersavage fits into */ -#define BCI_ENABLE_TWISTER 0 +/* prosavage, supersavage?, DDR, 2000 */ +#define BCI_ENABLE_2000 0 #define S3_BIG_ENDIAN 4 #define S3_LITTLE_ENDIAN 0 Index: savage_dri.c =================================================================== RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/savage/savage_dri.c,v retrieving revision 1.3 diff -u -r1.3 savage_dri.c --- savage_dri.c 23 Mar 2004 21:11:37 -0000 1.3 +++ savage_dri.c 30 Mar 2004 18:56:22 -0000 @@ -1303,24 +1303,25 @@ pSAVAGEDRI->frontPitch = pSAVAGEDRIServer->frontPitch; pSAVAGEDRI->IsfrontTiled = psav->bTiled; /* AGD: was 0 */ + if(pSAVAGEDRI->cpp==2) + TileStride = (pSAVAGEDRI->width+63)&(~63); + else + TileStride = (pSAVAGEDRI->width+31)&(~31); + if(pSAVAGEDRI->IsfrontTiled) { - if(pSAVAGEDRI->cpp==2) - TileStride = (pSAVAGEDRI->width+63)&(~63); - else - TileStride = (pSAVAGEDRI->width+31)&(~31); - if ((psav->Chipset == S3_TWISTER) - || (psav->Chipset == S3_PROSAVAGE) + if ((psav->Chipset == S3_PROSAVAGE) || (psav->Chipset == S3_PROSAVAGEDDR) || (psav->Chipset == S3_SUPERSAVAGE)) { - pSAVAGEDRI->frontBitmapDesc = 0x10000000 | /* block write disabled */ + pSAVAGEDRI->frontBitmapDesc = BCI_BD_BW_DISABLE | /* block write disabled */ (1<<24) | /* destination tile format */ (pScrn->bitsPerPixel<<16) | /* bpp */ TileStride; /* stride */ - } else { - pSAVAGEDRI->frontBitmapDesc = 0x10000000 | /* block write disabled */ + pSAVAGEDRI->frontPitch = TileStride; + } else { /* twister seems to use this format too */ + pSAVAGEDRI->frontBitmapDesc = BCI_BD_BW_DISABLE | /* block write disabled */ ((pSAVAGEDRI->cpp==2)? BCI_BD_TILE_16:BCI_BD_TILE_32) | /*16/32 bpp tile format */ (pScrn->bitsPerPixel<<16) | /* bpp */ @@ -1330,70 +1331,51 @@ } else { - pSAVAGEDRI->frontBitmapDesc = 0x10000000 | /* AGD: block write should be disabled: was 0x00000000 */ + pSAVAGEDRI->frontBitmapDesc = BCI_BD_BW_DISABLE | pScrn->bitsPerPixel<<16 | pSAVAGEDRI->width; } - - pSAVAGEDRI->backOffset = pSAVAGEDRIServer->backOffset; - pSAVAGEDRI->backbufferSize = pSAVAGEDRIServer->backbufferSize; - pSAVAGEDRI->backbuffer = psav->FrameBufferBase + - pSAVAGEDRI->backOffset; - pSAVAGEDRI->backPitch = pSAVAGEDRIServer->backPitch; { - if(pSAVAGEDRI->cpp==2) - TileStride = (pSAVAGEDRI->width+63)&(~63); - else - TileStride = (pSAVAGEDRI->width+31)&(~31); - if ((psav->Chipset == S3_TWISTER) - || (psav->Chipset == S3_PROSAVAGE) + if ((psav->Chipset == S3_PROSAVAGE) || (psav->Chipset == S3_PROSAVAGEDDR) || (psav->Chipset == S3_SUPERSAVAGE)) /* AGD: supersavage may work like savage4/MX/IX, I just don't know. */ { /* It's here since the 2D driver sets it up like prosavage */ - pSAVAGEDRI->backBitmapDesc = 0x10000000 | + pSAVAGEDRI->backBitmapDesc = BCI_BD_BW_DISABLE | (1<<24) | (pScrn->bitsPerPixel<<16) | TileStride; - } else { - pSAVAGEDRI->backBitmapDesc = 0x10000000 | + pSAVAGEDRI->depthBitmapDesc = BCI_BD_BW_DISABLE | + (1<<24) | + (pScrn->bitsPerPixel<<16) | + TileStride; + } else { /* twister seems to use this format too */ + pSAVAGEDRI->backBitmapDesc = BCI_BD_BW_DISABLE | ((pSAVAGEDRI->cpp==2)? BCI_BD_TILE_16:BCI_BD_TILE_32) | (pScrn->bitsPerPixel<<16) | TileStride; + pSAVAGEDRI->depthBitmapDesc = BCI_BD_BW_DISABLE | + ((pSAVAGEDRI->zpp==2)? + BCI_BD_TILE_16:BCI_BD_TILE_32) | + (pScrn->bitsPerPixel<<16) | + TileStride; } } + pSAVAGEDRI->backOffset = pSAVAGEDRIServer->backOffset; + pSAVAGEDRI->backbufferSize = pSAVAGEDRIServer->backbufferSize; + pSAVAGEDRI->backbuffer = psav->FrameBufferBase + + pSAVAGEDRI->backOffset; + pSAVAGEDRI->backPitch = pSAVAGEDRIServer->backPitch; + pSAVAGEDRI->depthOffset = pSAVAGEDRIServer->depthOffset; pSAVAGEDRI->depthbufferSize = pSAVAGEDRIServer->depthbufferSize; pSAVAGEDRI->depthbuffer = psav->FrameBufferBase + pSAVAGEDRI->depthOffset; pSAVAGEDRI->depthPitch = pSAVAGEDRIServer->depthPitch; - { - if(pSAVAGEDRI->zpp==2) - TileStride = (pSAVAGEDRI->width+63)&(~63); - else - TileStride = (pSAVAGEDRI->width+31)&(~31); - - if ((psav->Chipset == S3_TWISTER) - || (psav->Chipset == S3_PROSAVAGE) - || (psav->Chipset == S3_PROSAVAGEDDR) - || (psav->Chipset == S3_SUPERSAVAGE)) - { - pSAVAGEDRI->depthBitmapDesc = 0x10000000 | - (1<<24) | - (pScrn->bitsPerPixel<<16) | - TileStride; - } else { - pSAVAGEDRI->depthBitmapDesc = 0x10000000 | - ((pSAVAGEDRI->zpp==2)? - BCI_BD_TILE_16:BCI_BD_TILE_32) | - (pScrn->bitsPerPixel<<16) | - TileStride; - } - } pSAVAGEDRI->textureOffset = pSAVAGEDRIServer->textureOffset; pSAVAGEDRI->textures = psav->FrameBufferBase + Index: savage_driver.c =================================================================== RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/savage/savage_driver.c,v retrieving revision 1.22 diff -u -r1.22 savage_driver.c --- savage_driver.c 26 Mar 2004 22:20:40 -0000 1.22 +++ savage_driver.c 30 Mar 2004 18:56:23 -0000 @@ -1310,16 +1310,14 @@ * The Savage4 and ProSavage have COB coherency bugs which render * the buffer useless. */ - /* - psav->cobIndex = 2; - psav->cobSize = 0x8000 << psav->cobIndex; - */ psav->cobIndex = 0; psav->cobSize = 0; } else { /* We use 128kB for the COB on all other chips. */ psav->cobSize = 0x20000; - if (S3_SAVAGE3D_SERIES(psav->Chipset)) { + if (S3_SAVAGE3D_SERIES(psav->Chipset) + || (psav->Chipset == S3_TWISTER)) /* twister seems to use 7 */ + { psav->cobIndex = 7; /* rev.A savage4 also uses 7 */ } else { psav->cobIndex = 2; Index: savage_regs.h =================================================================== RCS file: /cvs/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v retrieving revision 1.10 diff -u -r1.10 savage_regs.h --- savage_regs.h 2 Mar 2004 18:15:45 -0000 1.10 +++ savage_regs.h 30 Mar 2004 18:56:24 -0000 @@ -3,6 +3,77 @@ #ifndef _SAVAGE_REGS_H #define _SAVAGE_REGS_H +/* + * A lesson in savage engines + * + * The various incarnations of the savage engines are a complicated story. + * I've done some research and wrote this little guide to help clarify things. + * There are 3 basic parts to the savage - 2D, 3D, and streams. + * There are 3 basic 2D cores: Savage3D, Savage4, 2000. + * There are 3 basic 3D cores: Savage3D, Savage4, 2000. + * There are 3 basic Streams engines: old, new/mobile, 2000. + * + * ****** 2D Cores ****** + * The different 2D cores have slightly different COB and bitmap descriptor layouts + * among other things. The 2D core breakdown looks like this: + * + * "Savage3D" 2D core: + * - Savage 3D + * - Savage MX + * - Savage IX + * + * "Savage4" 2D core: + * - Savage4 + * - Twister + * + * "2000" 2D core: + * - ProSavage + * - ProSavage DDR + * - Savage 2000 + * - SuperSavage + * + * ****** 3D Cores ****** + * The "savage4" 3D core has some slight variations within the series, but is + * the same for the most part. The 3D core breakdown looks like this: + * + * "Savage3D" 3D core: + * - Savage 3D + * - Savage MX + * - Savage IX + * + * "Savage4" 3D core: + * - Savage4 + * - Twister + * - ProSavage + * - ProSavage DDR + * - SuperSavage + * + * "2000" 3D core: + * - Savage 2000 + * + * ****** Streams Engines ****** + * The "new/mobile" streams engine is really basically just 2 old streams engines + * with some tweaks; one for each head (the mobile savages support dualhead). I + * suspect the "2000" streams engine is similar to the "old" engine, but with some + * tweaks from the "new" one. The streams breakdown looks like this: + * + * "old" streams: + * - Savage 3D + * - Savage4 + * - Twister + * - ProSavage + * - ProSavage DDR + * + * "new/mobile" streams: + * - Savage MX + * - Savage IX + * - SuperSavage + * + * "2000" streams: + * - Savage 2000 + * + */ + /* These are here until xf86PciInfo.h is updated. */ #ifndef PCI_CHIP_S3TWISTER_P