On Mon, 2003-02-03 at 17:34, Alan Cox wrote:
> On Mon, 2003-02-03 at 15:02, Keith Whitwell wrote:
> > >
> > > -#define COMMIT_RING() do { \
> > > - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
> > > +#define COMMIT_RING() do { \
> > > + /* read from PCI bus to ensure correct posting */ \
> > > + RADEON_READ( RADEON_CP_RB_WPTR ); \
> > > + RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
> > > + RADEON_READ( RADEON_CP_RB_WPTR ); \
> > > } while (0)
> >
> > Ouch. Put a conditional around that at least, so that not everybody suffers...
>
> PCI posting applies to all platforms. However I'm trying to understand what this
> is trying to do. The final read has an effect in that it ensures that the WPTR is
> written not left posted for an undefined time. What does the previous one achieve.
> Is there some kind of synchronization requirement against the GART/main memory ?
That's my understanding, we need to make sure the chip reads from the
ring what we wrote to it.
--
Earthling Michel D�nzer (MrCooper)/ Debian GNU/Linux (powerpc) developer
XFree86 and DRI project member / CS student, Free Software enthusiast
-------------------------------------------------------
This SF.NET email is sponsored by:
SourceForge Enterprise Edition + IBM + LinuxWorld = Something 2 See!
http://www.vasoftware.com
_______________________________________________
Dri-devel mailing list
[EMAIL PROTECTED]
https://lists.sourceforge.net/lists/listinfo/dri-devel
