On Fri, Jan 03, 2003 at 03:41:00AM +0200, Ville Syrj�l� wrote:
> On Thu, Jan 02, 2003 at 04:02:12PM -0800, Ian Romanick wrote:
> > So, I've done some more tinkering with the vblank IRQ on the G400. By
> > putting debug messages in a few places I managed to determine that
> > interrupts are not happening.
>
> Is the linecomp register programmed correctly?
I just had look at the source and it doesn't look right. Perhaps I'm
missing something but it looks like the linecomp is programmed as follows:
bit 10 = 0
bits 8-9 = 1
bits 0-7 = vertical display end lower 8 bits
This should put the linecomp value somewhere between 768 and 1023. So I
don't understand why modes with vdispend > 1023 aren't split in two like
they should be. And vline interrupts should be generated too. If bit 10
was 1 I'd understand the current situation but now I'm just confused. Any
ideas?
I've attached a completely untested patch which should fix the linecomp
value.
--
Ville Syrj�l�
[EMAIL PROTECTED]
http://www.sci.fi/~syrjala/
--- mga_dacG.c Fri Jan 3 18:23:49 2003
+++ mga_dacG.c Fri Jan 3 18:30:23 2003
@@ -479,7 +479,9 @@
pReg->ExtVga[2] = ((vt & 0xc00) >> 10) |
((vd & 0x400) >> 8) |
((vd & 0xc00) >> 7) |
- ((vs & 0xc00) >> 5);
+ ((vs & 0xc00) >> 5) |
+ ((vd & 0x400) >> 3);
+
if (pLayout->bitsPerPixel == 24)
pReg->ExtVga[3] = (((1 << BppShift) * 3) - 1) | 0x80;
else
@@ -498,11 +500,11 @@
((vd & 0x100) >> 7 ) |
((vs & 0x100) >> 6 ) |
((vd & 0x100) >> 5 ) |
- 0x10 |
+ ((vd & 0x100) >> 4 ) |
((vt & 0x200) >> 4 ) |
((vd & 0x200) >> 3 ) |
((vs & 0x200) >> 2 );
- pVga->CRTC[9] = ((vd & 0x200) >> 4) | 0x40;
+ pVga->CRTC[9] = ((vd & 0x200) >> 4) | ((vd & 0x200) >> 3);
pVga->CRTC[16] = vs & 0xFF;
pVga->CRTC[17] = (ve & 0x0F) | 0x20;
pVga->CRTC[18] = vd & 0xFF;
