Tim Smith wrote: > On Tuesday 28 May 2002 8:40 am, Keith Whitwell scribed numinously:" > >>Tim Smith wrote: >> >>>I've done some more digging and it would appear to send an enormous >>>amount of commands via radeon_cp_cmdbuf, all ending up going via >>>radeon_emit_packet3_cliprect. Actually I don't think it's such a huge >>>number compared to other calls (32 commands), except that this time the >>>loop gets called with nbox=4 so it emits everything 4 times, and runs >>>out of FIFO. >>> >>If it's really a fifo issue, I may have a solution for this in terms of >>only writing the ring tail register once per ioctl. >> > > Is it in a testable state? If you mail me a patch I'll test it tonight and > report. > > Assuming that RADEON_CP_RB_WPTR is the ring tail register, I count at least > 20 writes to it on this one call, and 16 on the previous "clear" (also with > nbox=4). And there are 13 consecutive calls to radeon_emit_packet3_cliprect > with nbox=4 before it locks, making a total of 260 writes from one call to > radeon_cp_cmdbuf.
It's committed on the tcl branch now (it's also a minor optimization). Keith _______________________________________________________________ Don't miss the 2002 Sprint PCS Application Developer's Conference August 25-28 in Las Vegas -- http://devcon.sprintpcs.com/adp/index.cfm _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
